1 /*
2 * ASPEED Ast27x0 SSP SoC
3 *
4 * Copyright (C) 2025 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/qdev-clock.h"
15 #include "hw/misc/unimp.h"
16 #include "hw/arm/aspeed_soc.h"
17
18 #define AST2700_SSP_RAM_SIZE (32 * MiB)
19
20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
21 [ASPEED_DEV_SRAM] = 0x00000000,
22 [ASPEED_DEV_INTC] = 0x72100000,
23 [ASPEED_DEV_SCU] = 0x72C02000,
24 [ASPEED_DEV_SCUIO] = 0x74C02000,
25 [ASPEED_DEV_UART0] = 0x74C33000,
26 [ASPEED_DEV_UART1] = 0x74C33100,
27 [ASPEED_DEV_UART2] = 0x74C33200,
28 [ASPEED_DEV_UART3] = 0x74C33300,
29 [ASPEED_DEV_UART4] = 0x72C1A000,
30 [ASPEED_DEV_INTCIO] = 0x74C18000,
31 [ASPEED_DEV_IPC0] = 0x72C1C000,
32 [ASPEED_DEV_IPC1] = 0x74C39000,
33 [ASPEED_DEV_UART5] = 0x74C33400,
34 [ASPEED_DEV_UART6] = 0x74C33500,
35 [ASPEED_DEV_UART7] = 0x74C33600,
36 [ASPEED_DEV_UART8] = 0x74C33700,
37 [ASPEED_DEV_UART9] = 0x74C33800,
38 [ASPEED_DEV_UART10] = 0x74C33900,
39 [ASPEED_DEV_UART11] = 0x74C33A00,
40 [ASPEED_DEV_UART12] = 0x74C33B00,
41 [ASPEED_DEV_TIMER1] = 0x72C10000,
42 };
43
44 static const int aspeed_soc_ast27x0ssp_irqmap[] = {
45 [ASPEED_DEV_SCU] = 12,
46 [ASPEED_DEV_UART0] = 164,
47 [ASPEED_DEV_UART1] = 164,
48 [ASPEED_DEV_UART2] = 164,
49 [ASPEED_DEV_UART3] = 164,
50 [ASPEED_DEV_UART4] = 8,
51 [ASPEED_DEV_UART5] = 164,
52 [ASPEED_DEV_UART6] = 164,
53 [ASPEED_DEV_UART7] = 164,
54 [ASPEED_DEV_UART8] = 164,
55 [ASPEED_DEV_UART9] = 164,
56 [ASPEED_DEV_UART10] = 164,
57 [ASPEED_DEV_UART11] = 164,
58 [ASPEED_DEV_UART12] = 164,
59 [ASPEED_DEV_TIMER1] = 16,
60 };
61
62 /* SSPINT 164 */
63 static const int ast2700_ssp132_ssp164_intcmap[] = {
64 [ASPEED_DEV_UART0] = 7,
65 [ASPEED_DEV_UART1] = 8,
66 [ASPEED_DEV_UART2] = 9,
67 [ASPEED_DEV_UART3] = 10,
68 [ASPEED_DEV_UART5] = 11,
69 [ASPEED_DEV_UART6] = 12,
70 [ASPEED_DEV_UART7] = 13,
71 [ASPEED_DEV_UART8] = 14,
72 [ASPEED_DEV_UART9] = 15,
73 [ASPEED_DEV_UART10] = 16,
74 [ASPEED_DEV_UART11] = 17,
75 [ASPEED_DEV_UART12] = 18,
76 };
77
78 struct nvic_intc_irq_info {
79 int irq;
80 int intc_idx;
81 int orgate_idx;
82 const int *ptr;
83 };
84
85 static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
86 {160, 1, 0, NULL},
87 {161, 1, 1, NULL},
88 {162, 1, 2, NULL},
89 {163, 1, 3, NULL},
90 {164, 1, 4, ast2700_ssp132_ssp164_intcmap},
91 {165, 1, 5, NULL},
92 {166, 1, 6, NULL},
93 {167, 1, 7, NULL},
94 {168, 1, 8, NULL},
95 {169, 1, 9, NULL},
96 {128, 0, 1, NULL},
97 {129, 0, 2, NULL},
98 {130, 0, 3, NULL},
99 {131, 0, 4, NULL},
100 {132, 0, 5, ast2700_ssp132_ssp164_intcmap},
101 {133, 0, 6, NULL},
102 {134, 0, 7, NULL},
103 {135, 0, 8, NULL},
104 {136, 0, 9, NULL},
105 };
106
aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState * s,int dev)107 static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int dev)
108 {
109 Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
110 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
111
112 int or_idx;
113 int idx;
114 int i;
115
116 for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
117 if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
118 assert(ast2700_ssp_intcmap[i].ptr);
119 or_idx = ast2700_ssp_intcmap[i].orgate_idx;
120 idx = ast2700_ssp_intcmap[i].intc_idx;
121 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
122 ast2700_ssp_intcmap[i].ptr[dev]);
123 }
124 }
125
126 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
127 }
128
aspeed_soc_ast27x0ssp_init(Object * obj)129 static void aspeed_soc_ast27x0ssp_init(Object *obj)
130 {
131 Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
132 AspeedSoCState *s = ASPEED_SOC(obj);
133 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
134 int i;
135
136 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
137 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
138 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
139 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
140
141 for (i = 0; i < sc->uarts_num; i++) {
142 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
143 }
144
145 object_initialize_child(obj, "intc0", &a->intc[0],
146 TYPE_ASPEED_2700SSP_INTC);
147 object_initialize_child(obj, "intc1", &a->intc[1],
148 TYPE_ASPEED_2700SSP_INTCIO);
149
150 object_initialize_child(obj, "timerctrl", &s->timerctrl,
151 TYPE_UNIMPLEMENTED_DEVICE);
152 object_initialize_child(obj, "ipc0", &a->ipc[0],
153 TYPE_UNIMPLEMENTED_DEVICE);
154 object_initialize_child(obj, "ipc1", &a->ipc[1],
155 TYPE_UNIMPLEMENTED_DEVICE);
156 object_initialize_child(obj, "scuio", &a->scuio,
157 TYPE_UNIMPLEMENTED_DEVICE);
158 }
159
aspeed_soc_ast27x0ssp_realize(DeviceState * dev_soc,Error ** errp)160 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
161 {
162 Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
163 AspeedSoCState *s = ASPEED_SOC(dev_soc);
164 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
165 DeviceState *armv7m;
166 g_autofree char *sram_name = NULL;
167 int i;
168
169 if (!clock_has_source(s->sysclk)) {
170 error_setg(errp, "sysclk clock must be wired up by the board code");
171 return;
172 }
173
174 /* AST27X0 SSP Core */
175 armv7m = DEVICE(&a->armv7m);
176 qdev_prop_set_uint32(armv7m, "num-irq", 256);
177 qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
178 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
179 object_property_set_link(OBJECT(&a->armv7m), "memory",
180 OBJECT(s->memory), &error_abort);
181 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
182
183 sram_name = g_strdup_printf("aspeed.dram.%d",
184 CPU(a->armv7m.cpu)->cpu_index);
185
186 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
187 errp)) {
188 return;
189 }
190 memory_region_add_subregion(s->memory,
191 sc->memmap[ASPEED_DEV_SRAM],
192 &s->sram);
193
194 /* SCU */
195 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
196 return;
197 }
198 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
199
200 /* INTC */
201 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
202 return;
203 }
204
205 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
206 sc->memmap[ASPEED_DEV_INTC]);
207
208 /* INTCIO */
209 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
210 return;
211 }
212
213 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
214 sc->memmap[ASPEED_DEV_INTCIO]);
215
216 /* irq source orgates -> INTC0 */
217 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
218 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
219 qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
220 }
221 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
222 assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
223 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
224 qdev_get_gpio_in(DEVICE(&a->armv7m),
225 ast2700_ssp_intcmap[i].irq));
226 }
227 /* irq source orgates -> INTCIO */
228 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
229 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
230 qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
231 }
232 /* INTCIO -> INTC */
233 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
234 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
235 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
236 }
237 /* UART */
238 if (!aspeed_soc_uart_realize(s, errp)) {
239 return;
240 }
241
242 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
243 "aspeed.timerctrl",
244 sc->memmap[ASPEED_DEV_TIMER1], 0x200);
245 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
246 "aspeed.ipc0",
247 sc->memmap[ASPEED_DEV_IPC0], 0x1000);
248 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
249 "aspeed.ipc1",
250 sc->memmap[ASPEED_DEV_IPC1], 0x1000);
251 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
252 "aspeed.scuio",
253 sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
254 }
255
aspeed_soc_ast27x0ssp_class_init(ObjectClass * klass,const void * data)256 static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *data)
257 {
258 static const char * const valid_cpu_types[] = {
259 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
260 NULL
261 };
262 DeviceClass *dc = DEVICE_CLASS(klass);
263 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
264
265 /* Reason: The Aspeed SoC can only be instantiated from a board */
266 dc->user_creatable = false;
267 dc->realize = aspeed_soc_ast27x0ssp_realize;
268
269 sc->valid_cpu_types = valid_cpu_types;
270 sc->silicon_rev = AST2700_A1_SILICON_REV;
271 sc->sram_size = AST2700_SSP_RAM_SIZE;
272 sc->spis_num = 0;
273 sc->ehcis_num = 0;
274 sc->wdts_num = 0;
275 sc->macs_num = 0;
276 sc->uarts_num = 13;
277 sc->uarts_base = ASPEED_DEV_UART0;
278 sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
279 sc->memmap = aspeed_soc_ast27x0ssp_memmap;
280 sc->num_cpus = 1;
281 sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
282 }
283
284 static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
285 {
286 .name = TYPE_ASPEED27X0SSP_SOC,
287 .parent = TYPE_ASPEED_SOC,
288 .instance_size = sizeof(Aspeed27x0SSPSoCState),
289 .instance_init = aspeed_soc_ast27x0ssp_init,
290 .class_init = aspeed_soc_ast27x0ssp_class_init,
291 },
292 };
293
294 DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
295