| #
6d0d9add |
| 05-May-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-aspeed-20250505' of https://github.com/legoater/qemu into staging
aspeed queue:
* Fixed AST2700 SPI model issues
* Updated SDK images
* Added FW support to the AST2700 EVB machines
Merge tag 'pull-aspeed-20250505' of https://github.com/legoater/qemu into staging
aspeed queue:
* Fixed AST2700 SPI model issues
* Updated SDK images
* Added FW support to the AST2700 EVB machines
* Introduced an AST27x0 multi-SoC machine
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# gpg: Signature made Mon 05 May 2025 05:05:15 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250505' of https://github.com/legoater/qemu: (24 commits)
docs: Add support for ast2700fc machine
tests/function/aspeed: Add functional test for ast2700fc
hw/arm: Introduce ASPEED AST2700 A1 full core machine
hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC
hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
hw/intc/aspeed: Add support for AST2700 TSP INTC
hw/intc/aspeed: Add support for AST2700 SSP INTC
aspeed: ast27x0: Correct hex notation for device addresses
aspeed: ast27x0: Map unimplemented devices in SoC memory
docs/system/arm/aspeed: Support vbootrom for AST2700
docs/system/arm/aspeed: move AST2700 content to new section
tests/functional/aspeed: Add to test vbootrom for AST2700
hw/arm/aspeed: Add support for loading vbootrom image via "-bios"
hw/arm/aspeed_ast27x0 Introduce vbootrom memory region
tests/functional/aspeed: extract boot and login sequence into helper function
tests/functional/aspeed: Update test ASPEED SDK v09.06
tests/functional/aspeed: Move I2C test into shared helper for AST2700 reuse
hw/arm/aspeed_ast27x0: Rename variable sram_name to name in ast2700 realize
tests/functional/aspeed: Update test ASPEED SDK v03.00 for AST1030
tests/functional/aspeed: Update test ASPEED SDK v09.06 for AST2600
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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|
| #
541da260 |
| 02-May-2025 |
Steven Lee <steven_lee@aspeedtech.com> |
hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- In
hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A1 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.
Difference from AST2700:
- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I924bf1a657f1e83f9e16d6673713f4a06ecdb496
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-6-steven_lee@aspeedtech.com
[ clg: removed local 'Error* err' in aspeed_soc_ast27x0ssp_realize() ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
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