xref: /qemu/include/hw/intc/aspeed_intc.h (revision 6d0d9add0d98effc7045466249921a09845225ac)
1 /*
2  * ASPEED INTC Controller
3  *
4  * Copyright (C) 2024 ASPEED Technology Inc.
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 #ifndef ASPEED_INTC_H
9 #define ASPEED_INTC_H
10 
11 #include "hw/sysbus.h"
12 #include "qom/object.h"
13 #include "hw/or-irq.h"
14 
15 #define TYPE_ASPEED_INTC "aspeed.intc"
16 #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
17 #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
18 #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
19 #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
20 #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
21 #define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
22 
23 OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
24 
25 #define ASPEED_INTC_MAX_INPINS 10
26 #define ASPEED_INTC_MAX_OUTPINS 19
27 
28 typedef struct AspeedINTCIRQ {
29     int inpin_idx;
30     int outpin_idx;
31     int num_outpins;
32     uint32_t enable_reg;
33     uint32_t status_reg;
34 } AspeedINTCIRQ;
35 
36 struct AspeedINTCState {
37     /*< private >*/
38     SysBusDevice parent_obj;
39 
40     /*< public >*/
41     MemoryRegion iomem;
42     MemoryRegion iomem_container;
43 
44     uint32_t *regs;
45     OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
46     qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
47 
48     uint32_t enable[ASPEED_INTC_MAX_INPINS];
49     uint32_t mask[ASPEED_INTC_MAX_INPINS];
50     uint32_t pending[ASPEED_INTC_MAX_INPINS];
51 };
52 
53 struct AspeedINTCClass {
54     SysBusDeviceClass parent_class;
55 
56     uint32_t num_lines;
57     uint32_t num_inpins;
58     uint32_t num_outpins;
59     uint64_t mem_size;
60     uint64_t nr_regs;
61     uint64_t reg_offset;
62     const MemoryRegionOps *reg_ops;
63     const AspeedINTCIRQ *irq_table;
64     int irq_table_count;
65 };
66 
67 #endif /* ASPEED_INTC_H */
68