1 /*
2 * ASPEED SoC 27x0 family
3 *
4 * Copyright (C) 2024 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * Implementation extracted from the AST2600 and adapted for AST27x0.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/misc/unimp.h"
15 #include "hw/arm/aspeed_soc.h"
16 #include "hw/arm/bsa.h"
17 #include "qemu/module.h"
18 #include "qemu/error-report.h"
19 #include "hw/i2c/aspeed_i2c.h"
20 #include "net/net.h"
21 #include "system/system.h"
22 #include "hw/intc/arm_gicv3.h"
23 #include "qobject/qlist.h"
24 #include "qemu/log.h"
25
26 #define AST2700_SOC_IO_SIZE 0x00FE0000
27 #define AST2700_SOC_IOMEM_SIZE 0x01000000
28 #define AST2700_SOC_DPMCU_SIZE 0x00040000
29 #define AST2700_SOC_LTPI_SIZE 0x01000000
30
31 static const hwaddr aspeed_soc_ast2700_memmap[] = {
32 [ASPEED_DEV_VBOOTROM] = 0x00000000,
33 [ASPEED_DEV_IOMEM] = 0x00020000,
34 [ASPEED_DEV_SRAM] = 0x10000000,
35 [ASPEED_DEV_DPMCU] = 0x11000000,
36 [ASPEED_DEV_IOMEM0] = 0x12000000,
37 [ASPEED_DEV_EHCI1] = 0x12061000,
38 [ASPEED_DEV_EHCI2] = 0x12063000,
39 [ASPEED_DEV_HACE] = 0x12070000,
40 [ASPEED_DEV_EMMC] = 0x12090000,
41 [ASPEED_DEV_INTC] = 0x12100000,
42 [ASPEED_GIC_DIST] = 0x12200000,
43 [ASPEED_GIC_REDIST] = 0x12280000,
44 [ASPEED_DEV_SDMC] = 0x12C00000,
45 [ASPEED_DEV_SCU] = 0x12C02000,
46 [ASPEED_DEV_RTC] = 0x12C0F000,
47 [ASPEED_DEV_TIMER1] = 0x12C10000,
48 [ASPEED_DEV_SLI] = 0x12C17000,
49 [ASPEED_DEV_UART4] = 0x12C1A000,
50 [ASPEED_DEV_IOMEM1] = 0x14000000,
51 [ASPEED_DEV_FMC] = 0x14000000,
52 [ASPEED_DEV_SPI0] = 0x14010000,
53 [ASPEED_DEV_SPI1] = 0x14020000,
54 [ASPEED_DEV_SPI2] = 0x14030000,
55 [ASPEED_DEV_MII1] = 0x14040000,
56 [ASPEED_DEV_MII2] = 0x14040008,
57 [ASPEED_DEV_MII3] = 0x14040010,
58 [ASPEED_DEV_ETH1] = 0x14050000,
59 [ASPEED_DEV_ETH2] = 0x14060000,
60 [ASPEED_DEV_ETH3] = 0x14070000,
61 [ASPEED_DEV_SDHCI] = 0x14080000,
62 [ASPEED_DEV_EHCI3] = 0x14121000,
63 [ASPEED_DEV_EHCI4] = 0x14123000,
64 [ASPEED_DEV_ADC] = 0x14C00000,
65 [ASPEED_DEV_SCUIO] = 0x14C02000,
66 [ASPEED_DEV_GPIO] = 0x14C0B000,
67 [ASPEED_DEV_I2C] = 0x14C0F000,
68 [ASPEED_DEV_INTCIO] = 0x14C18000,
69 [ASPEED_DEV_SLIIO] = 0x14C1E000,
70 [ASPEED_DEV_VUART] = 0x14C30000,
71 [ASPEED_DEV_UART0] = 0x14C33000,
72 [ASPEED_DEV_UART1] = 0x14C33100,
73 [ASPEED_DEV_UART2] = 0x14C33200,
74 [ASPEED_DEV_UART3] = 0x14C33300,
75 [ASPEED_DEV_UART5] = 0x14C33400,
76 [ASPEED_DEV_UART6] = 0x14C33500,
77 [ASPEED_DEV_UART7] = 0x14C33600,
78 [ASPEED_DEV_UART8] = 0x14C33700,
79 [ASPEED_DEV_UART9] = 0x14C33800,
80 [ASPEED_DEV_UART10] = 0x14C33900,
81 [ASPEED_DEV_UART11] = 0x14C33A00,
82 [ASPEED_DEV_UART12] = 0x14C33B00,
83 [ASPEED_DEV_WDT] = 0x14C37000,
84 [ASPEED_DEV_SPI_BOOT] = 0x100000000,
85 [ASPEED_DEV_LTPI] = 0x300000000,
86 [ASPEED_DEV_SDRAM] = 0x400000000,
87 };
88
89 #define AST2700_MAX_IRQ 256
90
91 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
92 static const int aspeed_soc_ast2700a0_irqmap[] = {
93 [ASPEED_DEV_SDMC] = 0,
94 [ASPEED_DEV_HACE] = 4,
95 [ASPEED_DEV_XDMA] = 5,
96 [ASPEED_DEV_UART4] = 8,
97 [ASPEED_DEV_SCU] = 12,
98 [ASPEED_DEV_RTC] = 13,
99 [ASPEED_DEV_EMMC] = 15,
100 [ASPEED_DEV_TIMER1] = 16,
101 [ASPEED_DEV_TIMER2] = 17,
102 [ASPEED_DEV_TIMER3] = 18,
103 [ASPEED_DEV_TIMER4] = 19,
104 [ASPEED_DEV_TIMER5] = 20,
105 [ASPEED_DEV_TIMER6] = 21,
106 [ASPEED_DEV_TIMER7] = 22,
107 [ASPEED_DEV_TIMER8] = 23,
108 [ASPEED_DEV_DP] = 28,
109 [ASPEED_DEV_EHCI1] = 33,
110 [ASPEED_DEV_EHCI2] = 37,
111 [ASPEED_DEV_LPC] = 128,
112 [ASPEED_DEV_IBT] = 128,
113 [ASPEED_DEV_KCS] = 128,
114 [ASPEED_DEV_ADC] = 130,
115 [ASPEED_DEV_GPIO] = 130,
116 [ASPEED_DEV_I2C] = 130,
117 [ASPEED_DEV_FMC] = 131,
118 [ASPEED_DEV_WDT] = 131,
119 [ASPEED_DEV_PWM] = 131,
120 [ASPEED_DEV_I3C] = 131,
121 [ASPEED_DEV_UART0] = 132,
122 [ASPEED_DEV_UART1] = 132,
123 [ASPEED_DEV_UART2] = 132,
124 [ASPEED_DEV_UART3] = 132,
125 [ASPEED_DEV_UART5] = 132,
126 [ASPEED_DEV_UART6] = 132,
127 [ASPEED_DEV_UART7] = 132,
128 [ASPEED_DEV_UART8] = 132,
129 [ASPEED_DEV_UART9] = 132,
130 [ASPEED_DEV_UART10] = 132,
131 [ASPEED_DEV_UART11] = 132,
132 [ASPEED_DEV_UART12] = 132,
133 [ASPEED_DEV_ETH1] = 132,
134 [ASPEED_DEV_ETH2] = 132,
135 [ASPEED_DEV_ETH3] = 132,
136 [ASPEED_DEV_PECI] = 133,
137 [ASPEED_DEV_SDHCI] = 133,
138 };
139
140 static const int aspeed_soc_ast2700a1_irqmap[] = {
141 [ASPEED_DEV_SDMC] = 0,
142 [ASPEED_DEV_HACE] = 4,
143 [ASPEED_DEV_XDMA] = 5,
144 [ASPEED_DEV_UART4] = 8,
145 [ASPEED_DEV_SCU] = 12,
146 [ASPEED_DEV_RTC] = 13,
147 [ASPEED_DEV_EMMC] = 15,
148 [ASPEED_DEV_TIMER1] = 16,
149 [ASPEED_DEV_TIMER2] = 17,
150 [ASPEED_DEV_TIMER3] = 18,
151 [ASPEED_DEV_TIMER4] = 19,
152 [ASPEED_DEV_TIMER5] = 20,
153 [ASPEED_DEV_TIMER6] = 21,
154 [ASPEED_DEV_TIMER7] = 22,
155 [ASPEED_DEV_TIMER8] = 23,
156 [ASPEED_DEV_DP] = 28,
157 [ASPEED_DEV_EHCI1] = 33,
158 [ASPEED_DEV_EHCI2] = 37,
159 [ASPEED_DEV_LPC] = 192,
160 [ASPEED_DEV_IBT] = 192,
161 [ASPEED_DEV_KCS] = 192,
162 [ASPEED_DEV_I2C] = 194,
163 [ASPEED_DEV_ADC] = 194,
164 [ASPEED_DEV_GPIO] = 194,
165 [ASPEED_DEV_FMC] = 195,
166 [ASPEED_DEV_WDT] = 195,
167 [ASPEED_DEV_PWM] = 195,
168 [ASPEED_DEV_I3C] = 195,
169 [ASPEED_DEV_UART0] = 196,
170 [ASPEED_DEV_UART1] = 196,
171 [ASPEED_DEV_UART2] = 196,
172 [ASPEED_DEV_UART3] = 196,
173 [ASPEED_DEV_UART5] = 196,
174 [ASPEED_DEV_UART6] = 196,
175 [ASPEED_DEV_UART7] = 196,
176 [ASPEED_DEV_UART8] = 196,
177 [ASPEED_DEV_UART9] = 196,
178 [ASPEED_DEV_UART10] = 196,
179 [ASPEED_DEV_UART11] = 196,
180 [ASPEED_DEV_UART12] = 196,
181 [ASPEED_DEV_ETH1] = 196,
182 [ASPEED_DEV_ETH2] = 196,
183 [ASPEED_DEV_ETH3] = 196,
184 [ASPEED_DEV_PECI] = 197,
185 [ASPEED_DEV_SDHCI] = 197,
186 };
187
188 /* GICINT 128 */
189 /* GICINT 192 */
190 static const int ast2700_gic128_gic192_intcmap[] = {
191 [ASPEED_DEV_LPC] = 0,
192 [ASPEED_DEV_IBT] = 2,
193 [ASPEED_DEV_KCS] = 4,
194 };
195
196 /* GICINT 129 */
197 /* GICINT 193 */
198
199 /* GICINT 130 */
200 /* GICINT 194 */
201 static const int ast2700_gic130_gic194_intcmap[] = {
202 [ASPEED_DEV_I2C] = 0,
203 [ASPEED_DEV_ADC] = 16,
204 [ASPEED_DEV_GPIO] = 18,
205 };
206
207 /* GICINT 131 */
208 /* GICINT 195 */
209 static const int ast2700_gic131_gic195_intcmap[] = {
210 [ASPEED_DEV_I3C] = 0,
211 [ASPEED_DEV_WDT] = 16,
212 [ASPEED_DEV_FMC] = 25,
213 [ASPEED_DEV_PWM] = 29,
214 };
215
216 /* GICINT 132 */
217 /* GICINT 196 */
218 static const int ast2700_gic132_gic196_intcmap[] = {
219 [ASPEED_DEV_ETH1] = 0,
220 [ASPEED_DEV_ETH2] = 1,
221 [ASPEED_DEV_ETH3] = 2,
222 [ASPEED_DEV_UART0] = 7,
223 [ASPEED_DEV_UART1] = 8,
224 [ASPEED_DEV_UART2] = 9,
225 [ASPEED_DEV_UART3] = 10,
226 [ASPEED_DEV_UART5] = 11,
227 [ASPEED_DEV_UART6] = 12,
228 [ASPEED_DEV_UART7] = 13,
229 [ASPEED_DEV_UART8] = 14,
230 [ASPEED_DEV_UART9] = 15,
231 [ASPEED_DEV_UART10] = 16,
232 [ASPEED_DEV_UART11] = 17,
233 [ASPEED_DEV_UART12] = 18,
234 [ASPEED_DEV_EHCI3] = 28,
235 [ASPEED_DEV_EHCI4] = 29,
236 };
237
238 /* GICINT 133 */
239 /* GICINT 197 */
240 static const int ast2700_gic133_gic197_intcmap[] = {
241 [ASPEED_DEV_SDHCI] = 1,
242 [ASPEED_DEV_PECI] = 4,
243 };
244
245 /* GICINT 128 ~ 136 */
246 /* GICINT 192 ~ 201 */
247 struct gic_intc_irq_info {
248 int irq;
249 int intc_idx;
250 int orgate_idx;
251 const int *ptr;
252 };
253
254 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
255 {192, 1, 0, ast2700_gic128_gic192_intcmap},
256 {193, 1, 1, NULL},
257 {194, 1, 2, ast2700_gic130_gic194_intcmap},
258 {195, 1, 3, ast2700_gic131_gic195_intcmap},
259 {196, 1, 4, ast2700_gic132_gic196_intcmap},
260 {197, 1, 5, ast2700_gic133_gic197_intcmap},
261 {198, 1, 6, NULL},
262 {199, 1, 7, NULL},
263 {200, 1, 8, NULL},
264 {201, 1, 9, NULL},
265 {128, 0, 1, ast2700_gic128_gic192_intcmap},
266 {129, 0, 2, NULL},
267 {130, 0, 3, ast2700_gic130_gic194_intcmap},
268 {131, 0, 4, ast2700_gic131_gic195_intcmap},
269 {132, 0, 5, ast2700_gic132_gic196_intcmap},
270 {133, 0, 6, ast2700_gic133_gic197_intcmap},
271 {134, 0, 7, NULL},
272 {135, 0, 8, NULL},
273 {136, 0, 9, NULL},
274 };
275
aspeed_soc_ast2700_get_irq(AspeedSoCState * s,int dev)276 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
277 {
278 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
279 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
280 int or_idx;
281 int idx;
282 int i;
283
284 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
285 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
286 assert(ast2700_gic_intcmap[i].ptr);
287 or_idx = ast2700_gic_intcmap[i].orgate_idx;
288 idx = ast2700_gic_intcmap[i].intc_idx;
289 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
290 ast2700_gic_intcmap[i].ptr[dev]);
291 }
292 }
293
294 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
295 }
296
aspeed_soc_ast2700_get_irq_index(AspeedSoCState * s,int dev,int index)297 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
298 int index)
299 {
300 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
301 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
302 int or_idx;
303 int idx;
304 int i;
305
306 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
307 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
308 assert(ast2700_gic_intcmap[i].ptr);
309 or_idx = ast2700_gic_intcmap[i].orgate_idx;
310 idx = ast2700_gic_intcmap[i].intc_idx;
311 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
312 ast2700_gic_intcmap[i].ptr[dev] + index);
313 }
314 }
315
316 /*
317 * Invalid OR gate index, device IRQ should be between 128 to 136
318 * and 192 to 201.
319 */
320 g_assert_not_reached();
321 }
322
aspeed_ram_capacity_read(void * opaque,hwaddr addr,unsigned int size)323 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
324 unsigned int size)
325 {
326 qemu_log_mask(LOG_GUEST_ERROR,
327 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n",
328 __func__, addr);
329 return 0;
330 }
331
aspeed_ram_capacity_write(void * opaque,hwaddr addr,uint64_t data,unsigned int size)332 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
333 unsigned int size)
334 {
335 AspeedSoCState *s = ASPEED_SOC(opaque);
336 ram_addr_t ram_size;
337 MemTxResult result;
338
339 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
340 &error_abort);
341
342 assert(ram_size > 0);
343
344 /*
345 * Emulate ddr capacity hardware behavior.
346 * If writes the data to the address which is beyond the ram size,
347 * it would write the data to the "address % ram_size".
348 */
349 address_space_stl_le(&s->dram_as, addr % ram_size, data,
350 MEMTXATTRS_UNSPECIFIED, &result);
351
352 if (result != MEMTX_OK) {
353 qemu_log_mask(LOG_GUEST_ERROR,
354 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx
355 ", data :0x%" PRIx64 "\n",
356 __func__, addr % ram_size, data);
357 }
358 }
359
360 static const MemoryRegionOps aspeed_ram_capacity_ops = {
361 .read = aspeed_ram_capacity_read,
362 .write = aspeed_ram_capacity_write,
363 .endianness = DEVICE_LITTLE_ENDIAN,
364 .impl.min_access_size = 4,
365 .valid = {
366 .min_access_size = 4,
367 .max_access_size = 4,
368 },
369 };
370
371 /*
372 * SDMC should be realized first to get correct RAM size and max size
373 * values
374 */
aspeed_soc_ast2700_dram_init(DeviceState * dev,Error ** errp)375 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
376 {
377 ram_addr_t ram_size, max_ram_size;
378 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
379 AspeedSoCState *s = ASPEED_SOC(dev);
380 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
381
382 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
383 &error_abort);
384 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
385 &error_abort);
386
387 memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
388 ram_size);
389 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
390 address_space_init(&s->dram_as, s->dram_mr, "dram");
391
392 /*
393 * Add a memory region beyond the RAM region to emulate
394 * ddr capacity hardware behavior.
395 */
396 if (ram_size < max_ram_size) {
397 memory_region_init_io(&a->dram_empty, OBJECT(s),
398 &aspeed_ram_capacity_ops, s,
399 "ram-empty", max_ram_size - ram_size);
400
401 memory_region_add_subregion(s->memory,
402 sc->memmap[ASPEED_DEV_SDRAM] + ram_size,
403 &a->dram_empty);
404 }
405
406 memory_region_add_subregion(s->memory,
407 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
408 return true;
409 }
410
aspeed_soc_ast2700_init(Object * obj)411 static void aspeed_soc_ast2700_init(Object *obj)
412 {
413 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
414 AspeedSoCState *s = ASPEED_SOC(obj);
415 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
416 int i;
417 char socname[8];
418 char typename[64];
419
420 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
421 g_assert_not_reached();
422 }
423
424 for (i = 0; i < sc->num_cpus; i++) {
425 object_initialize_child(obj, "cpu[*]", &a->cpu[i],
426 aspeed_soc_cpu_type(sc));
427 }
428
429 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
430
431 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
432 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
433 sc->silicon_rev);
434 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
435 "hw-strap1");
436 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
437 "hw-prot-key");
438
439 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
440 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
441 sc->silicon_rev);
442 /*
443 * There is one hw-strap1 register in the SCU (CPU DIE) and another
444 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design
445 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the
446 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and
447 * sets the value in the SCUIO hw-strap1 register.
448 */
449 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio),
450 "hw-strap1");
451
452 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
453 object_initialize_child(obj, "fmc", &s->fmc, typename);
454
455 for (i = 0; i < sc->spis_num; i++) {
456 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname);
457 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
458 }
459
460 for (i = 0; i < sc->ehcis_num; i++) {
461 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
462 TYPE_PLATFORM_EHCI);
463 }
464
465 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
466 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
467 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
468 "ram-size");
469
470 for (i = 0; i < sc->wdts_num; i++) {
471 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
472 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
473 }
474
475 for (i = 0; i < sc->macs_num; i++) {
476 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
477 TYPE_FTGMAC100);
478
479 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
480 }
481
482 for (i = 0; i < sc->uarts_num; i++) {
483 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
484 }
485
486 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
487 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
488 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
489 object_initialize_child(obj, "intcio", &a->intc[1],
490 TYPE_ASPEED_2700_INTCIO);
491
492 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
493 object_initialize_child(obj, "adc", &s->adc, typename);
494
495 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
496 object_initialize_child(obj, "i2c", &s->i2c, typename);
497
498 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
499 object_initialize_child(obj, "gpio", &s->gpio, typename);
500
501 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
502
503 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
504 object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
505 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort);
506
507 /* Init sd card slot class here so that they're under the correct parent */
508 object_initialize_child(obj, "sd-controller.sdhci",
509 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
510
511 object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
512 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
513
514 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
515 TYPE_SYSBUS_SDHCI);
516
517 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
518 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
519
520 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
521 object_initialize_child(obj, "hace", &s->hace, typename);
522 object_initialize_child(obj, "dpmcu", &s->dpmcu,
523 TYPE_UNIMPLEMENTED_DEVICE);
524 object_initialize_child(obj, "ltpi", &s->ltpi,
525 TYPE_UNIMPLEMENTED_DEVICE);
526 object_initialize_child(obj, "iomem", &s->iomem,
527 TYPE_UNIMPLEMENTED_DEVICE);
528 object_initialize_child(obj, "iomem0", &s->iomem0,
529 TYPE_UNIMPLEMENTED_DEVICE);
530 object_initialize_child(obj, "iomem1", &s->iomem1,
531 TYPE_UNIMPLEMENTED_DEVICE);
532 }
533
534 /*
535 * ASPEED ast2700 has 0x0 as cluster ID
536 *
537 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1
538 */
aspeed_calc_affinity(int cpu)539 static uint64_t aspeed_calc_affinity(int cpu)
540 {
541 return (0x0 << ARM_AFF1_SHIFT) | cpu;
542 }
543
aspeed_soc_ast2700_gic_realize(DeviceState * dev,Error ** errp)544 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
545 {
546 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
547 AspeedSoCState *s = ASPEED_SOC(dev);
548 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
549 SysBusDevice *gicbusdev;
550 DeviceState *gicdev;
551 QList *redist_region_count;
552 int i;
553
554 gicbusdev = SYS_BUS_DEVICE(&a->gic);
555 gicdev = DEVICE(&a->gic);
556 qdev_prop_set_uint32(gicdev, "revision", 3);
557 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
558 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL);
559
560 redist_region_count = qlist_new();
561 qlist_append_int(redist_region_count, sc->num_cpus);
562 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
563
564 if (!sysbus_realize(gicbusdev, errp)) {
565 return false;
566 }
567
568 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0,
569 sc->memmap[ASPEED_GIC_DIST]);
570 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1,
571 sc->memmap[ASPEED_GIC_REDIST]);
572
573 for (i = 0; i < sc->num_cpus; i++) {
574 DeviceState *cpudev = DEVICE(&a->cpu[i]);
575 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL;
576
577 const int timer_irq[] = {
578 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
579 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
580 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
581 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
582 };
583 int j;
584
585 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
586 qdev_connect_gpio_out(cpudev, j,
587 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j]));
588 }
589
590 qemu_irq irq = qdev_get_gpio_in(gicdev,
591 intidbase + ARCH_GIC_MAINT_IRQ);
592 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
593 0, irq);
594 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
595 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ));
596
597 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
598 sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
599 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
600 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
601 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
602 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
603 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
604 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus,
605 qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
606 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus,
607 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
608 }
609
610 return true;
611 }
612
aspeed_soc_ast2700_realize(DeviceState * dev,Error ** errp)613 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
614 {
615 int i;
616 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
617 AspeedSoCState *s = ASPEED_SOC(dev);
618 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
619 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]);
620 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]);
621 g_autofree char *name = NULL;
622 qemu_irq irq;
623
624 /* Default boot region (SPI memory or ROMs) */
625 memory_region_init(&s->spi_boot_container, OBJECT(s),
626 "aspeed.spi_boot_container", 0x400000000);
627 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
628 &s->spi_boot_container);
629
630 /* CPU */
631 for (i = 0; i < sc->num_cpus; i++) {
632 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
633 aspeed_calc_affinity(i), &error_abort);
634
635 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
636 &error_abort);
637 object_property_set_link(OBJECT(&a->cpu[i]), "memory",
638 OBJECT(s->memory), &error_abort);
639
640 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
641 return;
642 }
643 }
644
645 /* GIC */
646 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) {
647 return;
648 }
649
650 /* INTC */
651 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
652 return;
653 }
654
655 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
656 sc->memmap[ASPEED_DEV_INTC]);
657
658 /* INTCIO */
659 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
660 return;
661 }
662
663 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
664 sc->memmap[ASPEED_DEV_INTCIO]);
665
666 /* irq sources -> orgates -> INTC */
667 for (i = 0; i < ic->num_inpins; i++) {
668 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
669 qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
670 }
671
672 /* INTC -> GIC192 - GIC201 */
673 /* INTC -> GIC128 - GIC136 */
674 for (i = 0; i < ic->num_outpins; i++) {
675 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
676 qdev_get_gpio_in(DEVICE(&a->gic),
677 ast2700_gic_intcmap[i].irq));
678 }
679
680 /* irq source -> orgates -> INTCIO */
681 for (i = 0; i < icio->num_inpins; i++) {
682 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
683 qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
684 }
685
686 /* INTCIO -> INTC */
687 for (i = 0; i < icio->num_outpins; i++) {
688 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
689 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
690 }
691
692 /* SRAM */
693 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
694 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
695 errp)) {
696 return;
697 }
698 memory_region_add_subregion(s->memory,
699 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
700
701 /* VBOOTROM */
702 if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
703 0x20000, errp)) {
704 return;
705 }
706 memory_region_add_subregion(s->memory,
707 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
708
709 /* SCU */
710 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
711 return;
712 }
713 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
714
715 /* SCU1 */
716 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
717 return;
718 }
719 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
720 sc->memmap[ASPEED_DEV_SCUIO]);
721
722 /* UART */
723 if (!aspeed_soc_uart_realize(s, errp)) {
724 return;
725 }
726
727 /* FMC, The number of CS is set at the board level */
728 object_property_set_int(OBJECT(&s->fmc), "dram-base",
729 sc->memmap[ASPEED_DEV_SDRAM],
730 &error_abort);
731 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
732 &error_abort);
733 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
734 return;
735 }
736 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
737 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
738 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
739 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
740 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
741
742 /* Set up an alias on the FMC CE0 region (boot default) */
743 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
744 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
745 fmc0_mmio, 0, memory_region_size(fmc0_mmio));
746 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
747
748 /* SPI */
749 for (i = 0; i < sc->spis_num; i++) {
750 object_property_set_link(OBJECT(&s->spi[i]), "dram",
751 OBJECT(s->dram_mr), &error_abort);
752 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
753 return;
754 }
755 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
756 sc->memmap[ASPEED_DEV_SPI0 + i]);
757 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
758 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
759 }
760
761 /* EHCI */
762 for (i = 0; i < sc->ehcis_num; i++) {
763 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
764 return;
765 }
766 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
767 sc->memmap[ASPEED_DEV_EHCI1 + i]);
768 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
769 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
770 }
771
772 /*
773 * SDMC - SDRAM Memory Controller
774 * The SDMC controller is unlocked at SPL stage.
775 * At present, only supports to emulate booting
776 * start from u-boot stage. Set SDMC controller
777 * unlocked by default. It is a temporarily solution.
778 */
779 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
780 &error_abort);
781 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
782 return;
783 }
784 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
785 sc->memmap[ASPEED_DEV_SDMC]);
786
787 /* RAM */
788 if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
789 return;
790 }
791
792 /* Net */
793 for (i = 0; i < sc->macs_num; i++) {
794 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
795 &error_abort);
796 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true,
797 &error_abort);
798 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
799 return;
800 }
801 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
802 sc->memmap[ASPEED_DEV_ETH1 + i]);
803 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
804 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
805
806 object_property_set_link(OBJECT(&s->mii[i]), "nic",
807 OBJECT(&s->ftgmac100[i]), &error_abort);
808 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
809 return;
810 }
811
812 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
813 sc->memmap[ASPEED_DEV_MII1 + i]);
814 }
815
816 /* Watch dog */
817 for (i = 0; i < sc->wdts_num; i++) {
818 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
819 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
820
821 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
822 &error_abort);
823 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
824 return;
825 }
826 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
827 }
828
829 /* SLI */
830 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) {
831 return;
832 }
833 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]);
834
835 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) {
836 return;
837 }
838 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0,
839 sc->memmap[ASPEED_DEV_SLIIO]);
840
841 /* ADC */
842 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
843 return;
844 }
845 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
846 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
847 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
848
849 /* I2C */
850 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
851 &error_abort);
852 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
853 return;
854 }
855 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
856 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
857 /*
858 * The AST2700 I2C controller has one source INTC per bus.
859 *
860 * For AST2700 A0:
861 * I2C bus interrupts are connected to the OR gate from bit 0 to bit
862 * 15, and the OR gate output pin is connected to the input pin of
863 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to
864 * the GIC.
865 *
866 * For AST2700 A1:
867 * I2C bus interrupts are connected to the OR gate from bit 0 to bit
868 * 15, and the OR gate output pin is connected to the input pin of
869 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected
870 * to the INTC (CPU Die) input pin, and its output pin is connected
871 * to the GIC.
872 *
873 * I2C bus 0 is connected to the OR gate at bit 0.
874 * I2C bus 15 is connected to the OR gate at bit 15.
875 */
876 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
877 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
878 }
879
880 /* GPIO */
881 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
882 return;
883 }
884 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
885 sc->memmap[ASPEED_DEV_GPIO]);
886 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
887 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
888
889 /* RTC */
890 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
891 return;
892 }
893 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
894 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
895 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
896
897 /* SDHCI */
898 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
899 return;
900 }
901 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
902 sc->memmap[ASPEED_DEV_SDHCI]);
903 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
904 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
905
906 /* eMMC */
907 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
908 return;
909 }
910 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
911 sc->memmap[ASPEED_DEV_EMMC]);
912 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
913 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
914
915 /* Timer */
916 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
917 &error_abort);
918 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
919 return;
920 }
921 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
922 sc->memmap[ASPEED_DEV_TIMER1]);
923 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
924 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
925 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
926 }
927
928 /* HACE */
929 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
930 &error_abort);
931 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
932 return;
933 }
934 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
935 sc->memmap[ASPEED_DEV_HACE]);
936 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
937 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
938
939 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu),
940 "aspeed.dpmcu",
941 sc->memmap[ASPEED_DEV_DPMCU],
942 AST2700_SOC_DPMCU_SIZE);
943 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi),
944 "aspeed.ltpi",
945 sc->memmap[ASPEED_DEV_LTPI],
946 AST2700_SOC_LTPI_SIZE);
947 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem),
948 "aspeed.io",
949 sc->memmap[ASPEED_DEV_IOMEM],
950 AST2700_SOC_IO_SIZE);
951 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0),
952 "aspeed.iomem0",
953 sc->memmap[ASPEED_DEV_IOMEM0],
954 AST2700_SOC_IOMEM_SIZE);
955 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1),
956 "aspeed.iomem1",
957 sc->memmap[ASPEED_DEV_IOMEM1],
958 AST2700_SOC_IOMEM_SIZE);
959 }
960
aspeed_soc_ast2700a0_class_init(ObjectClass * oc,const void * data)961 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data)
962 {
963 static const char * const valid_cpu_types[] = {
964 ARM_CPU_TYPE_NAME("cortex-a35"),
965 NULL
966 };
967 DeviceClass *dc = DEVICE_CLASS(oc);
968 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
969
970 /* Reason: The Aspeed SoC can only be instantiated from a board */
971 dc->user_creatable = false;
972 dc->realize = aspeed_soc_ast2700_realize;
973
974 sc->valid_cpu_types = valid_cpu_types;
975 sc->silicon_rev = AST2700_A0_SILICON_REV;
976 sc->sram_size = 0x20000;
977 sc->spis_num = 3;
978 sc->ehcis_num = 2;
979 sc->wdts_num = 8;
980 sc->macs_num = 1;
981 sc->uarts_num = 13;
982 sc->num_cpus = 4;
983 sc->uarts_base = ASPEED_DEV_UART0;
984 sc->irqmap = aspeed_soc_ast2700a0_irqmap;
985 sc->memmap = aspeed_soc_ast2700_memmap;
986 sc->get_irq = aspeed_soc_ast2700_get_irq;
987 }
988
aspeed_soc_ast2700a1_class_init(ObjectClass * oc,const void * data)989 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
990 {
991 static const char * const valid_cpu_types[] = {
992 ARM_CPU_TYPE_NAME("cortex-a35"),
993 NULL
994 };
995 DeviceClass *dc = DEVICE_CLASS(oc);
996 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
997
998 /* Reason: The Aspeed SoC can only be instantiated from a board */
999 dc->user_creatable = false;
1000 dc->realize = aspeed_soc_ast2700_realize;
1001
1002 sc->valid_cpu_types = valid_cpu_types;
1003 sc->silicon_rev = AST2700_A1_SILICON_REV;
1004 sc->sram_size = 0x20000;
1005 sc->spis_num = 3;
1006 sc->ehcis_num = 4;
1007 sc->wdts_num = 8;
1008 sc->macs_num = 3;
1009 sc->uarts_num = 13;
1010 sc->num_cpus = 4;
1011 sc->uarts_base = ASPEED_DEV_UART0;
1012 sc->irqmap = aspeed_soc_ast2700a1_irqmap;
1013 sc->memmap = aspeed_soc_ast2700_memmap;
1014 sc->get_irq = aspeed_soc_ast2700_get_irq;
1015 }
1016
1017 static const TypeInfo aspeed_soc_ast27x0_types[] = {
1018 {
1019 .name = TYPE_ASPEED27X0_SOC,
1020 .parent = TYPE_ASPEED_SOC,
1021 .instance_size = sizeof(Aspeed27x0SoCState),
1022 .abstract = true,
1023 }, {
1024 .name = "ast2700-a0",
1025 .parent = TYPE_ASPEED27X0_SOC,
1026 .instance_init = aspeed_soc_ast2700_init,
1027 .class_init = aspeed_soc_ast2700a0_class_init,
1028 },
1029 {
1030 .name = "ast2700-a1",
1031 .parent = TYPE_ASPEED27X0_SOC,
1032 .instance_init = aspeed_soc_ast2700_init,
1033 .class_init = aspeed_soc_ast2700a1_class_init,
1034 },
1035 };
1036
1037 DEFINE_TYPES(aspeed_soc_ast27x0_types)
1038