1d831c5fdSJamin Lin /* 2d831c5fdSJamin Lin * ASPEED INTC Controller 3d831c5fdSJamin Lin * 4d831c5fdSJamin Lin * Copyright (C) 2024 ASPEED Technology Inc. 5d831c5fdSJamin Lin * 6d831c5fdSJamin Lin * SPDX-License-Identifier: GPL-2.0-or-later 7d831c5fdSJamin Lin */ 8d831c5fdSJamin Lin #ifndef ASPEED_INTC_H 9d831c5fdSJamin Lin #define ASPEED_INTC_H 10d831c5fdSJamin Lin 11d831c5fdSJamin Lin #include "hw/sysbus.h" 12d831c5fdSJamin Lin #include "qom/object.h" 13d831c5fdSJamin Lin #include "hw/or-irq.h" 14d831c5fdSJamin Lin 15d831c5fdSJamin Lin #define TYPE_ASPEED_INTC "aspeed.intc" 16d831c5fdSJamin Lin #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" 1738ba38d8SJamin Lin #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" 188872b671SSteven Lee #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" 198872b671SSteven Lee #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" 20*c528f10dSSteven Lee #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" 21*c528f10dSSteven Lee #define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp" 228872b671SSteven Lee 23d831c5fdSJamin Lin OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) 24d831c5fdSJamin Lin 259178ff91SJamin Lin #define ASPEED_INTC_MAX_INPINS 10 269178ff91SJamin Lin #define ASPEED_INTC_MAX_OUTPINS 19 27d831c5fdSJamin Lin 28ab24c6a2SJamin Lin typedef struct AspeedINTCIRQ { 29ab24c6a2SJamin Lin int inpin_idx; 30ab24c6a2SJamin Lin int outpin_idx; 31ab24c6a2SJamin Lin int num_outpins; 32ab24c6a2SJamin Lin uint32_t enable_reg; 33ab24c6a2SJamin Lin uint32_t status_reg; 34ab24c6a2SJamin Lin } AspeedINTCIRQ; 35ab24c6a2SJamin Lin 36d831c5fdSJamin Lin struct AspeedINTCState { 37d831c5fdSJamin Lin /*< private >*/ 38d831c5fdSJamin Lin SysBusDevice parent_obj; 39d831c5fdSJamin Lin 40d831c5fdSJamin Lin /*< public >*/ 41d831c5fdSJamin Lin MemoryRegion iomem; 42c5728c34SJamin Lin MemoryRegion iomem_container; 43c5728c34SJamin Lin 44563afea0SJamin Lin uint32_t *regs; 4563f3618fSJamin Lin OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; 4635c909cdSJamin Lin qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS]; 47d831c5fdSJamin Lin 4863f3618fSJamin Lin uint32_t enable[ASPEED_INTC_MAX_INPINS]; 4963f3618fSJamin Lin uint32_t mask[ASPEED_INTC_MAX_INPINS]; 5063f3618fSJamin Lin uint32_t pending[ASPEED_INTC_MAX_INPINS]; 51d831c5fdSJamin Lin }; 52d831c5fdSJamin Lin 53d831c5fdSJamin Lin struct AspeedINTCClass { 54d831c5fdSJamin Lin SysBusDeviceClass parent_class; 55d831c5fdSJamin Lin 56d831c5fdSJamin Lin uint32_t num_lines; 5763f3618fSJamin Lin uint32_t num_inpins; 5835c909cdSJamin Lin uint32_t num_outpins; 59c5728c34SJamin Lin uint64_t mem_size; 60b008465dSJamin Lin uint64_t nr_regs; 617ffee511SJamin Lin uint64_t reg_offset; 6228194d5dSJamin Lin const MemoryRegionOps *reg_ops; 63ab24c6a2SJamin Lin const AspeedINTCIRQ *irq_table; 64ab24c6a2SJamin Lin int irq_table_count; 65d831c5fdSJamin Lin }; 66d831c5fdSJamin Lin 67d831c5fdSJamin Lin #endif /* ASPEED_INTC_H */ 68