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/qemu/hw/char/
H A Dstm32l4x5_usart.c36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */
44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
46 FIELD(CR1, PCE, 10, 1) /* Parity control enable */
47 FIELD(CR1, PS, 9, 1) /* Parity selection */
[all …]
/qemu/hw/sd/
H A Dsdhci-internal.h54 #define SDHC_CMD_DATA_PRESENT (1 << 5)
55 #define SDHC_CMD_SUSPEND (1 << 6)
56 #define SDHC_CMD_RESUME (1 << 7)
57 #define SDHC_CMD_ABORT ((1 << 6)|(1 << 7))
58 #define SDHC_CMD_TYPE_MASK ((1 << 6)|(1 << 7))
63 /* ROC Response Register 1 0x0 */
87 FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1);
109 #define SDHC_POWER_ON (1 << 0)
110 FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3);
119 #define SDHC_WKUP_ON_INS (1 << 1)
[all …]
/qemu/tests/vmstate-static-checker-data/
H A Ddump2.json8 "minimum_version_id": 1,
12 "minimum_version_id": 1,
37 "version_id": 1,
38 "minimum_version_id": 1,
42 "minimum_version_id": 1,
52 "minimum_version_id": 1,
115 "field": "portsc[1]",
194 "version_id": 1,
195 "minimum_version_id": 1,
198 "version_id": 1,
[all …]
/qemu/tests/qemu-iotests/
H A D303.out1 Add bitmap 1
3 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
6 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
9 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
15 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
23 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
36 l1_size 1
[all …]
H A D060.out6 ERROR cluster 3 refcount=1 reference=3
8 1 errors were found on the image.
13 incompatible_features [1]
34 ERROR cluster 2 refcount=1 reference=2
41 incompatible_features [1]
43 ERROR cluster 2 refcount=1 reference=2
45 Repairing cluster 1 refcount=1 reference=0
46 Repairing cluster 2 refcount=2 reference=1
66 ERROR cluster 4 refcount=1 reference=2
67 Leaked cluster 9 refcount=1 reference=0
[all …]
H A D13128 status=1 # failure is the default!
34 trap "_cleanup; exit \$status" 0 1 2 3 15
58 { $QEMU_IO -c "read -P 0 $CLUSTER_HALF_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | …
59 echo == write more than 1 block in a row ==
60 { $QEMU_IO -c "write -P 0x11 $CLUSTER_HALF_SIZE $CLUSTER_DBL_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qe…
62 { $QEMU_IO -c "read -P 0x11 $CLUSTER_HALF_SIZE $CLUSTER_HALF_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qe…
63 echo == read exactly 1 block ==
64 { $QEMU_IO -c "read -P 0x11 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _f…
65 echo == read more than 1 block ==
66 { $QEMU_IO -c "read -P 0x11 $CLUSTER_HALF_SIZE $CLUSTER_DBL_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qem…
[all …]
/qemu/target/arm/
H A Dcpu.h36 #define EXCP_UDEF 1 /* undefined instruction */
66 #define ARMV7M_EXCP_RESET 1
106 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
114 s<2n+1> maps to the most significant half of d<n>
147 * Qn = regs[n].d[1]:regs[n].d[0]
148 * Dn = regs[n / 2].d[n & 1]
154 * Qn = regs[n].d[1]:regs[n].d[0]
203 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
206 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
224 * behaviour when FPCR.AH == 1: they don't update cumulative
[all …]
/qemu/hw/usb/
H A Dhcd-dwc3.c44 #define HOST_MODE 1
53 FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
54 FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
56 FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
57 FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
58 FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1)
59 FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1)
60 FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1)
61 FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1)
62 FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1)
[all …]
/qemu/bsd-user/arm/
H A Dtarget_arch_elf.h44 ARM_HWCAP_ARM_SWP = 1 << 0,
45 ARM_HWCAP_ARM_HALF = 1 << 1,
46 ARM_HWCAP_ARM_THUMB = 1 << 2,
47 ARM_HWCAP_ARM_26BIT = 1 << 3,
48 ARM_HWCAP_ARM_FAST_MULT = 1 << 4,
49 ARM_HWCAP_ARM_FPA = 1 << 5,
50 ARM_HWCAP_ARM_VFP = 1 << 6,
51 ARM_HWCAP_ARM_EDSP = 1 << 7,
52 ARM_HWCAP_ARM_JAVA = 1 << 8,
53 ARM_HWCAP_ARM_IWMMXT = 1 << 9,
[all …]
/qemu/target/arm/tcg/
H A Dsve.decode26 %imm6_22_5 22:1 5:5
32 %index3_22_19 22:1 19:2
33 %index3_19_11 19:2 11:1
34 %index2_20_11 20:1 11:1
107 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
114 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
190 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
208 # One register, pattern, and uint4+1.
231 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
233 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_bz.S7 _beqz a2, 1f
9 1:
10 movi a2, 1
11 _beqz a2, 1f
13 1:
19 movi a2, 1
20 _bnez a2, 1f
22 1:
24 _bnez a2, 1f
26 1:
[all …]
H A Dtest_break.S17 rsil a2, debug_level - 1
18 1:
28 movi a3, 1b
41 rsil a2, debug_level - 1
42 1:
52 movi a3, 1b
63 movi a2, 1f
65 movi a2, 1
68 1:
69 rsil a2, debug_level - 1
[all …]
/qemu/target/mips/tcg/
H A Ddsp_helper.c34 uint32_t uw[1];
35 int32_t sw[1];
45 uint64_t ul[1];
46 int64_t sl[1];
62 env->active_tc.DSPControl &= ~(1 << 13); in set_DSPControl_carryflag()
75 filter = ((0x01 << len) - 1) << 24; in set_DSPControl_24()
124 set_DSPControl_overflow_flag(1, 20, env); \
143 set_DSPControl_overflow_flag(1, 20, env); in mipsdsp_add_i16()
162 set_DSPControl_overflow_flag(1, 20, env); in mipsdsp_sat_add_i16()
181 set_DSPControl_overflow_flag(1, 20, env); in mipsdsp_sat_add_i32()
[all …]
/qemu/tests/tcg/hexagon/
H A Dfloat_convs.ref4 to int32: -1 (INVALID)
5 to int64: -1 (INVALID)
6 to uint32: -1 (INVALID)
7 to uint64: -1 (INVALID)
10 to int32: -1 (INVALID)
11 to int64: -1 (INVALID)
12 to uint32: -1 (INVALID)
13 to uint64: -1 (INVALID)
94 to int32: 1 (OK)
95 to int64: 1 (OK)
[all …]
H A Datomics.c34 "1: %0 = memw_locked(%2)\n\t" in atomic_inc32()
35 " %1 = add(%0, #1)\n\t" in atomic_inc32()
36 " memw_locked(%2, p0) = %1\n\t" in atomic_inc32()
37 " if (!p0) jump 1b\n\t" in atomic_inc32()
48 "1: %0 = memd_locked(%2)\n\t" in atomic_inc64()
49 " %1 = #1\n\t" in atomic_inc64()
50 " %1 = add(%0, %1)\n\t" in atomic_inc64()
51 " memd_locked(%2, p0) = %1\n\t" in atomic_inc64()
52 " if (!p0) jump 1b\n\t" in atomic_inc64()
63 "1: %0 = memw_locked(%2)\n\t" in atomic_dec32()
[all …]
/qemu/hw/net/can/
H A Dxlnx-zynqmp-can.c57 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
58 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
60 FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
61 FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
62 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
73 FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
74 FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
75 FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
76 FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
77 FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
[all …]
/qemu/hw/i386/
H A Dintel_iommu_internal.h103 #define DMAR_FRCD_REG_NR 1ULL /* Num of fault recording regs */
114 VTD_INTERRUPT_ADDR_FIRST + 1)
123 #define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */
127 #define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57)
131 #define VTD_TLB_IVT (1ULL << 63)
139 #define VTD_GCMD_TE (1UL << 31)
140 #define VTD_GCMD_SRTP (1UL << 30)
141 #define VTD_GCMD_SFL (1UL << 29)
142 #define VTD_GCMD_EAFL (1UL << 28)
143 #define VTD_GCMD_WBF (1UL << 27)
[all …]
/qemu/host/include/i386/host/
H A Dcpuinfo.h11 #define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
12 #define CPUINFO_OSXSAVE (1u << 1)
13 #define CPUINFO_MOVBE (1u << 2)
14 #define CPUINFO_LZCNT (1u << 3)
15 #define CPUINFO_POPCNT (1u << 4)
16 #define CPUINFO_BMI1 (1u << 5)
17 #define CPUINFO_BMI2 (1u << 6)
18 #define CPUINFO_SSE2 (1u << 7)
19 #define CPUINFO_AVX1 (1u << 9)
20 #define CPUINFO_AVX2 (1u << 10)
[all …]
/qemu/hw/nvram/
H A Dxlnx-versal-efuse-ctrl.c41 FIELD(CFG, SLVERR_ENABLE, 5, 1)
42 FIELD(CFG, MARGIN_RD, 2, 1)
43 FIELD(CFG, PGM_EN, 1, 1)
45 FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1)
46 FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1)
47 FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1)
48 FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
49 FIELD(STATUS, AES_CRC_PASS, 7, 1)
50 FIELD(STATUS, AES_CRC_DONE, 6, 1)
51 FIELD(STATUS, CACHE_DONE, 5, 1)
[all …]
/qemu/hw/net/
H A Dvmxnet3.h144 /* BAR 1 */
161 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
166 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
173 #define VMXNET3_IO_TYPE_VD 1
206 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
211 * Byte 1 : rsvd gen 13.len.8
217 * Byte 1 : 5.msscof.0 ext1 dtype
233 u32 ext1:1;
234 u32 dtype:1; /* descriptor type */
235 u32 rsvd:1;
[all …]
/qemu/target/s390x/
H A Dmachine.c66 .version_id = 1,
67 .minimum_version_id = 1,
71 VMSTATE_UINT64(env.vregs[1][0], S390CPU),
98 .version_id = 1,
99 .minimum_version_id = 1,
119 VMSTATE_UINT64(env.vregs[0][1], S390CPU),
120 VMSTATE_UINT64(env.vregs[1][1], S390CPU),
121 VMSTATE_UINT64(env.vregs[2][1], S390CPU),
122 VMSTATE_UINT64(env.vregs[3][1], S390CPU),
123 VMSTATE_UINT64(env.vregs[4][1], S390CPU),
[all …]
/qemu/target/loongarch/
H A Dcpu-csr.h20 FIELD(CSR_PRMD, PIE, 2, 1)
21 FIELD(CSR_PRMD, PWE, 3, 1)
24 FIELD(CSR_EUEN, FPE, 0, 1)
25 FIELD(CSR_EUEN, SXE, 1, 1)
26 FIELD(CSR_EUEN, ASXE, 2, 1)
27 FIELD(CSR_EUEN, BTE, 3, 1)
57 FIELD(CSR_TLBIDX, NE, 31, 1)
65 FIELD(TLBENTRY, V, 0, 1)
66 FIELD(TLBENTRY, D, 1, 1)
69 FIELD(TLBENTRY, G, 6, 1)
[all …]
/qemu/tcg/aarch64/
H A Dtcg-target-has.h26 #define TCG_TARGET_HAS_qemu_ldst_i128 1
29 #define TCG_TARGET_HAS_tst 1
31 #define TCG_TARGET_HAS_v64 1
32 #define TCG_TARGET_HAS_v128 1
35 #define TCG_TARGET_HAS_andc_vec 1
36 #define TCG_TARGET_HAS_orc_vec 1
40 #define TCG_TARGET_HAS_not_vec 1
41 #define TCG_TARGET_HAS_neg_vec 1
42 #define TCG_TARGET_HAS_abs_vec 1
46 #define TCG_TARGET_HAS_shi_vec 1
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h39 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
48 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
49 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
53 #define XCHAL_HAVE_DEBUG 1 /* debug option */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
58 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
59 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
61 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
[all …]
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h19 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
29 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
33 #define XCHAL_HAVE_DEBUG 1 /* debug option */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
36 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
37 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
38 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
39 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
40 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
[all …]

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