Lines Matching full:1
36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */
44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
46 FIELD(CR1, PCE, 10, 1) /* Parity control enable */
47 FIELD(CR1, PS, 9, 1) /* Parity selection */
48 FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */
49 FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */
50 FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */
51 FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */
52 FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */
53 FIELD(CR1, TE, 3, 1) /* Transmitter enable */
54 FIELD(CR1, RE, 2, 1) /* Receiver enable */
55 FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */
56 FIELD(CR1, UE, 0, 1) /* USART enable */
60 FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */
62 FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */
63 FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */
64 FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */
65 FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */
66 FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */
67 FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */
68 FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */
70 FIELD(CR2, CLKEN, 11, 1) /* Clock enable */
71 FIELD(CR2, CPOL, 10, 1) /* Clock polarity */
72 FIELD(CR2, CPHA, 9, 1) /* Clock phase */
73 FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */
74 FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */
75 FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */
76 FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */
80 FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */
81 FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */
84 FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */
85 FIELD(CR3, DEM, 14, 1) /* Driver enable mode */
86 FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */
87 FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */
88 FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */
89 FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */
90 FIELD(CR3, CTSE, 9, 1) /* CTS enable */
91 FIELD(CR3, RTSE, 8, 1) /* RTS enable */
92 FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */
93 FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */
94 FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */
95 FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */
96 FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */
97 FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */
98 FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */
99 FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */
109 FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */
110 FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */
111 FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */
112 FIELD(RQR, SBKRQ, 1, 1) /* Send break request */
113 FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */
116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */
117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */
118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */
121 FIELD(ISR, CMF, 17, 1) /* Character match flag */
122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */
123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */
124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */
125 FIELD(ISR, EOBF, 12, 1) /* End of block flag */
126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */
127 FIELD(ISR, CTS, 10, 1) /* CTS flag */
128 FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */
129 FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */
130 FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */
131 FIELD(ISR, TC, 6, 1) /* Transmission complete */
132 FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */
133 FIELD(ISR, IDLE, 4, 1) /* Idle line detected */
134 FIELD(ISR, ORE, 3, 1) /* Overrun error */
135 FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */
136 FIELD(ISR, FE, 1, 1) /* Framing Error */
137 FIELD(ISR, PE, 0, 1) /* Parity Error */
139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */
141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */
142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */
144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */
146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */
147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */
148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */
149 FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */
150 FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */
151 FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */
203 return 1; in stm32l4x5_usart_base_can_receive()
256 ret = qemu_chr_fe_write(&s->chr, &ch, 1); in usart_transmit()
309 stop_bits = 1; in stm32l4x5_update_params()
322 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { in stm32l4x5_update_params()
326 case 1: in stm32l4x5_update_params()
355 * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. in stm32l4x5_update_params()
360 usart_div = ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2; in stm32l4x5_update_params()
564 .version_id = 1,
565 .minimum_version_id = 1,