Lines Matching full:1
103 #define DMAR_FRCD_REG_NR 1ULL /* Num of fault recording regs */
114 VTD_INTERRUPT_ADDR_FIRST + 1)
123 #define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */
127 #define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57)
131 #define VTD_TLB_IVT (1ULL << 63)
139 #define VTD_GCMD_TE (1UL << 31)
140 #define VTD_GCMD_SRTP (1UL << 30)
141 #define VTD_GCMD_SFL (1UL << 29)
142 #define VTD_GCMD_EAFL (1UL << 28)
143 #define VTD_GCMD_WBF (1UL << 27)
144 #define VTD_GCMD_QIE (1UL << 26)
145 #define VTD_GCMD_IRE (1UL << 25)
146 #define VTD_GCMD_SIRTP (1UL << 24)
147 #define VTD_GCMD_CFI (1UL << 23)
150 #define VTD_GSTS_TES (1UL << 31)
151 #define VTD_GSTS_RTPS (1UL << 30)
152 #define VTD_GSTS_FLS (1UL << 29)
153 #define VTD_GSTS_AFLS (1UL << 28)
154 #define VTD_GSTS_WBFS (1UL << 27)
155 #define VTD_GSTS_QIES (1UL << 26)
156 #define VTD_GSTS_IRES (1UL << 25)
157 #define VTD_GSTS_IRTPS (1UL << 24)
158 #define VTD_GSTS_CFIS (1UL << 23)
161 #define VTD_CCMD_ICC (1ULL << 63)
162 #define VTD_CCMD_GLOBAL_INVL (1ULL << 61)
166 #define VTD_CCMD_GLOBAL_INVL_A (1ULL << 59)
175 #define VTD_RTADDR_SMT (1ULL << 10)
180 #define VTD_IRTA_EIME (1ULL << 11)
186 #define VTD_ECAP_QI (1ULL << 1)
187 #define VTD_ECAP_DT (1ULL << 2)
189 #define VTD_ECAP_IR (1ULL << 3)
190 #define VTD_ECAP_EIM (1ULL << 4)
191 #define VTD_ECAP_PT (1ULL << 6)
192 #define VTD_ECAP_SC (1ULL << 7)
194 #define VTD_ECAP_SRS (1ULL << 31)
195 #define VTD_ECAP_PASID (1ULL << 40)
196 #define VTD_ECAP_SMTS (1ULL << 43)
197 #define VTD_ECAP_SLTS (1ULL << 46)
198 #define VTD_ECAP_FLTS (1ULL << 47)
203 #define VTD_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40)
205 #define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
207 #define VTD_ADDRESS_SIZE(aw) (1ULL << (aw))
208 #define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16)
211 #define VTD_CAP_PSI (1ULL << 39)
212 #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
213 #define VTD_CAP_DRAIN_WRITE (1ULL << 54)
214 #define VTD_CAP_DRAIN_READ (1ULL << 55)
215 #define VTD_CAP_FS1GP (1ULL << 56)
217 #define VTD_CAP_CM (1ULL << 7)
219 #define VTD_PASID_ID_MASK ((1ULL << VTD_PASID_ID_SHIFT) - 1)
245 #define VTD_ICS_IWC 1UL
248 #define VTD_IECTL_IM (1UL << 31)
249 #define VTD_IECTL_IP (1UL << 30)
254 #define VTD_FSTS_IQE (1UL << 4)
255 #define VTD_FSTS_PPF (1UL << 1)
256 #define VTD_FSTS_PFO 1UL
259 #define VTD_FECTL_IM (1UL << 31)
260 #define VTD_FECTL_IP (1UL << 30)
264 #define VTD_FRCD_F (1ULL << 63)
265 #define VTD_FRCD_T (1ULL << 62)
278 VTD_FR_ROOT_ENTRY_P = 1, /* The Present(P) field of root-entry is 0 */
281 VTD_FR_ADDR_BEYOND_MGAW, /* Input-address above (2^x-1) */
331 VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/
350 uint64_t granularity:1; /* If set, it's global IR invalidation */
354 uint32_t granularity:1; /* If set, it's global IR invalidation */
379 #define VTD_INV_DESC_ALL_ONE -1ULL
394 #define VTD_INV_DESC_WAIT_SW (1ULL << 5)
395 #define VTD_INV_DESC_WAIT_IF (1ULL << 4)
396 #define VTD_INV_DESC_WAIT_FN (1ULL << 6)
403 #define VTD_INV_DESC_CC_GLOBAL (1ULL << 4)
413 #define VTD_INV_DESC_IOTLB_GLOBAL (1ULL << 4)
504 #define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT)
507 #define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
509 #define VTD_PAGE_MASK_2M (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
511 #define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
520 #define VTD_ROOT_ENTRY_P 1ULL
530 #define VTD_CONTEXT_ENTRY_P (1ULL << 0)
531 #define VTD_CONTEXT_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
534 #define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2)
560 #define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disable */
563 #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
566 #define VTD_PASID_ENTRY_P 1ULL
568 #define VTD_SM_PASID_ENTRY_FLT (1ULL << 6)
581 #define VTD_FL_P 1ULL
582 #define VTD_FL_RW (1ULL << 1)
583 #define VTD_FL_US (1ULL << 2)
584 #define VTD_FL_A (1ULL << 5)
585 #define VTD_FL_D (1ULL << 6)
593 #define VTD_SL_R 1ULL
594 #define VTD_SL_W (1ULL << 1)
596 #define VTD_SL_TM (1ULL << 62)
602 #define VTD_PT_LEVEL 1
604 #define VTD_PT_PAGE_SIZE_MASK (1ULL << 7)
605 #define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))