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19 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
29 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
33 #define XCHAL_HAVE_DEBUG 1 /* debug option */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
36 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
37 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
38 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
39 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
40 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
41 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */
43 #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU insns */
44 #define XCHAL_HAVE_L32R 1 /* L32R instruction */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
47 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
50 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
51 #define XCHAL_HAVE_ABS 1 /* ABS instruction */
54 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
55 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
57 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
58 #define XCHAL_NUM_CONTEXTS 1 /* */
61 #define XCHAL_HAVE_PRID 1 /* processor ID register */
62 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
64 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
66 #define XCHAL_HAVE_MAC16 1 /* MAC16 package */
82 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
83 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
101 #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
103 #define XCHAL_HW_REL_LX2 1
104 #define XCHAL_HW_REL_LX2_1 1
105 #define XCHAL_HW_REL_LX2_1_1 1
106 #define XCHAL_HW_CONFIGID_RELIABLE 1
109 #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
112 #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
128 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
144 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
157 #define XCHAL_ICACHE_LINE_LOCKABLE 1
158 #define XCHAL_DCACHE_LINE_LOCKABLE 1
182 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
183 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
184 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
185 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
193 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
204 /* Masks of interrupts at each range 1..n of interrupt levels: */
214 #define XCHAL_INT0_LEVEL 1
215 #define XCHAL_INT1_LEVEL 1
216 #define XCHAL_INT2_LEVEL 1
217 #define XCHAL_INT3_LEVEL 1
218 #define XCHAL_INT4_LEVEL 1
219 #define XCHAL_INT5_LEVEL 1
220 #define XCHAL_INT6_LEVEL 1
221 #define XCHAL_INT7_LEVEL 1
229 #define XCHAL_INT15_LEVEL 1
230 #define XCHAL_INT16_LEVEL 1
231 #define XCHAL_INT17_LEVEL 1
232 #define XCHAL_INT18_LEVEL 1
233 #define XCHAL_INT19_LEVEL 1
234 #define XCHAL_INT20_LEVEL 1
237 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
286 /* (There are many interrupts each at level(s) 1, 3.) */
299 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
300 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
301 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
302 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
303 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
304 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
309 #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
310 #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
311 #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
312 #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
313 #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
314 #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
323 number: 1 == XEA1 (old)
326 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
327 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
329 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
331 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
332 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
390 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
393 #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
402 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
408 #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
416 #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */