Lines Matching full:1
36 #define EXCP_UDEF 1 /* undefined instruction */
66 #define ARMV7M_EXCP_RESET 1
106 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
114 s<2n+1> maps to the most significant half of d<n>
147 * Qn = regs[n].d[1]:regs[n].d[0]
148 * Dn = regs[n / 2].d[n & 1]
154 * Qn = regs[n].d[1]:regs[n].d[0]
203 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
206 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
224 * behaviour when FPCR.AH == 1: they don't update cumulative
225 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and
294 uint32_t CF; /* 0 or 1 */
298 uint32_t QF; /* 0 or 1 */
344 union { /* MMU translation table base 1. */
495 uint64_t tpidrro_el[1];
559 uint64_t fgt_exec[1]; /* HFGITR */
677 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
678 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
793 env->features |= 1ULL << feature; in set_feature()
798 env->features &= ~(1ULL << feature); in unset_feature()
818 PSCI_OFF = 1,
825 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
826 * bytes, i.e. each bit number + 1 is the vector length in quadwords.
941 * 0 - disabled, 1 - smc, 2 - hvc
1205 * @target_el must be an EL implemented by the CPU between 1 and 3.
1257 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1307 #define SCTLR_M (1U << 0)
1308 #define SCTLR_A (1U << 1)
1309 #define SCTLR_C (1U << 2)
1310 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1311 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1312 #define SCTLR_SA (1U << 3) /* AArch64 only */
1313 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1314 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1315 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1316 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1317 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1318 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1319 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
1320 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1321 #define SCTLR_ITD (1U << 7) /* v8 onward */
1322 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1323 #define SCTLR_SED (1U << 8) /* v8 onward */
1324 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1325 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1326 #define SCTLR_F (1U << 10) /* up to v6 */
1327 #define SCTLR_SW (1U << 10) /* v7 */
1328 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1329 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1330 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1331 #define SCTLR_I (1U << 12)
1332 #define SCTLR_V (1U << 13) /* AArch32 only */
1333 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1334 #define SCTLR_RR (1U << 14) /* up to v7 */
1335 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1336 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1337 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1338 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1339 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1340 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1341 #define SCTLR_BR (1U << 17) /* PMSA only */
1342 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1343 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1344 #define SCTLR_WXN (1U << 19)
1345 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1346 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1347 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1348 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1349 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1350 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1351 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1352 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1353 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1354 #define SCTLR_VE (1U << 24) /* up to v7 */
1355 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1356 #define SCTLR_EE (1U << 25)
1357 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1358 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1359 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1360 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1361 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1362 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1363 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1364 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1365 #define SCTLR_TE (1U << 30) /* AArch32 only */
1366 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1367 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1368 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1369 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */
1370 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
1371 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1372 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1373 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1376 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1377 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1378 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1379 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
1381 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
1382 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
1383 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
1384 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */
1385 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
1386 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
1387 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
1388 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
1389 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
1390 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
1391 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1392 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
1395 #define CPSR_T (1U << 5)
1396 #define CPSR_F (1U << 6)
1397 #define CPSR_I (1U << 7)
1398 #define CPSR_A (1U << 8)
1399 #define CPSR_E (1U << 9)
1402 #define CPSR_IL (1U << 20)
1403 #define CPSR_DIT (1U << 21)
1404 #define CPSR_PAN (1U << 22)
1405 #define CPSR_SSBS (1U << 23)
1406 #define CPSR_J (1U << 24)
1408 #define CPSR_Q (1U << 27)
1409 #define CPSR_V (1U << 28)
1410 #define CPSR_C (1U << 29)
1411 #define CPSR_Z (1U << 30)
1412 #define CPSR_N (1U << 31)
1415 #define ISR_FS (1U << 9)
1416 #define ISR_IS (1U << 10)
1428 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1431 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1432 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1446 #define PSTATE_SP (1U)
1448 #define PSTATE_nRW (1U << 4)
1449 #define PSTATE_F (1U << 6)
1450 #define PSTATE_I (1U << 7)
1451 #define PSTATE_A (1U << 8)
1452 #define PSTATE_D (1U << 9)
1454 #define PSTATE_SSBS (1U << 12)
1455 #define PSTATE_ALLINT (1U << 13)
1456 #define PSTATE_IL (1U << 20)
1457 #define PSTATE_SS (1U << 21)
1458 #define PSTATE_PAN (1U << 22)
1459 #define PSTATE_UAO (1U << 23)
1460 #define PSTATE_DIT (1U << 24)
1461 #define PSTATE_TCO (1U << 25)
1462 #define PSTATE_V (1U << 28)
1463 #define PSTATE_C (1U << 29)
1464 #define PSTATE_Z (1U << 30)
1465 #define PSTATE_N (1U << 31)
1479 FIELD(SVCR, SM, 0, 1)
1480 FIELD(SVCR, ZA, 1, 1)
1484 FIELD(SMCR, FA64, 31, 1)
1515 env->CF = (val >> 29) & 1; in pstate_write()
1527 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1561 env->CF = (val >> 29) & 1; in xpsr_write()
1589 #define HCR_VM (1ULL << 0)
1590 #define HCR_SWIO (1ULL << 1)
1591 #define HCR_PTW (1ULL << 2)
1592 #define HCR_FMO (1ULL << 3)
1593 #define HCR_IMO (1ULL << 4)
1594 #define HCR_AMO (1ULL << 5)
1595 #define HCR_VF (1ULL << 6)
1596 #define HCR_VI (1ULL << 7)
1597 #define HCR_VSE (1ULL << 8)
1598 #define HCR_FB (1ULL << 9)
1600 #define HCR_DC (1ULL << 12)
1601 #define HCR_TWI (1ULL << 13)
1602 #define HCR_TWE (1ULL << 14)
1603 #define HCR_TID0 (1ULL << 15)
1604 #define HCR_TID1 (1ULL << 16)
1605 #define HCR_TID2 (1ULL << 17)
1606 #define HCR_TID3 (1ULL << 18)
1607 #define HCR_TSC (1ULL << 19)
1608 #define HCR_TIDCP (1ULL << 20)
1609 #define HCR_TACR (1ULL << 21)
1610 #define HCR_TSW (1ULL << 22)
1611 #define HCR_TPCP (1ULL << 23)
1612 #define HCR_TPU (1ULL << 24)
1613 #define HCR_TTLB (1ULL << 25)
1614 #define HCR_TVM (1ULL << 26)
1615 #define HCR_TGE (1ULL << 27)
1616 #define HCR_TDZ (1ULL << 28)
1617 #define HCR_HCD (1ULL << 29)
1618 #define HCR_TRVM (1ULL << 30)
1619 #define HCR_RW (1ULL << 31)
1620 #define HCR_CD (1ULL << 32)
1621 #define HCR_ID (1ULL << 33)
1622 #define HCR_E2H (1ULL << 34)
1623 #define HCR_TLOR (1ULL << 35)
1624 #define HCR_TERR (1ULL << 36)
1625 #define HCR_TEA (1ULL << 37)
1626 #define HCR_MIOCNCE (1ULL << 38)
1627 #define HCR_TME (1ULL << 39)
1628 #define HCR_APK (1ULL << 40)
1629 #define HCR_API (1ULL << 41)
1630 #define HCR_NV (1ULL << 42)
1631 #define HCR_NV1 (1ULL << 43)
1632 #define HCR_AT (1ULL << 44)
1633 #define HCR_NV2 (1ULL << 45)
1634 #define HCR_FWB (1ULL << 46)
1635 #define HCR_FIEN (1ULL << 47)
1636 #define HCR_GPF (1ULL << 48)
1637 #define HCR_TID4 (1ULL << 49)
1638 #define HCR_TICAB (1ULL << 50)
1639 #define HCR_AMVOFFEN (1ULL << 51)
1640 #define HCR_TOCU (1ULL << 52)
1641 #define HCR_ENSCXT (1ULL << 53)
1642 #define HCR_TTLBIS (1ULL << 54)
1643 #define HCR_TTLBOS (1ULL << 55)
1644 #define HCR_ATA (1ULL << 56)
1645 #define HCR_DCT (1ULL << 57)
1646 #define HCR_TID5 (1ULL << 58)
1647 #define HCR_TWEDEN (1ULL << 59)
1650 #define SCR_NS (1ULL << 0)
1651 #define SCR_IRQ (1ULL << 1)
1652 #define SCR_FIQ (1ULL << 2)
1653 #define SCR_EA (1ULL << 3)
1654 #define SCR_FW (1ULL << 4)
1655 #define SCR_AW (1ULL << 5)
1656 #define SCR_NET (1ULL << 6)
1657 #define SCR_SMD (1ULL << 7)
1658 #define SCR_HCE (1ULL << 8)
1659 #define SCR_SIF (1ULL << 9)
1660 #define SCR_RW (1ULL << 10)
1661 #define SCR_ST (1ULL << 11)
1662 #define SCR_TWI (1ULL << 12)
1663 #define SCR_TWE (1ULL << 13)
1664 #define SCR_TLOR (1ULL << 14)
1665 #define SCR_TERR (1ULL << 15)
1666 #define SCR_APK (1ULL << 16)
1667 #define SCR_API (1ULL << 17)
1668 #define SCR_EEL2 (1ULL << 18)
1669 #define SCR_EASE (1ULL << 19)
1670 #define SCR_NMEA (1ULL << 20)
1671 #define SCR_FIEN (1ULL << 21)
1672 #define SCR_ENSCXT (1ULL << 25)
1673 #define SCR_ATA (1ULL << 26)
1674 #define SCR_FGTEN (1ULL << 27)
1675 #define SCR_ECVEN (1ULL << 28)
1676 #define SCR_TWEDEN (1ULL << 29)
1678 #define SCR_TME (1ULL << 34)
1679 #define SCR_AMVOFFEN (1ULL << 35)
1680 #define SCR_ENAS0 (1ULL << 36)
1681 #define SCR_ADEN (1ULL << 37)
1682 #define SCR_HXEN (1ULL << 38)
1683 #define SCR_TRNDR (1ULL << 40)
1684 #define SCR_ENTP2 (1ULL << 41)
1685 #define SCR_GPF (1ULL << 48)
1686 #define SCR_NSE (1ULL << 62)
1707 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */
1708 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */
1709 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */
1710 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1711 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1712 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1713 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1714 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1715 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */
1716 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1718 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1721 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1722 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1723 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1733 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */
1734 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */
1735 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */
1736 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */
1737 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */
1738 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */
1739 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */
1740 #define FPSR_V (1 << 28) /* FP overflow flag */
1741 #define FPSR_C (1 << 29) /* FP carry flag */
1742 #define FPSR_Z (1 << 30) /* FP zero flag */
1743 #define FPSR_N (1 << 31) /* FP negative flag */
1804 #define ARM_VFP_FPSCR 1
1823 #define ARM_IWMMXT_wCon 1
1832 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1833 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1834 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1835 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1836 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1837 FIELD(V7M_CCR, STKALIGN, 9, 1)
1838 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1839 FIELD(V7M_CCR, DC, 16, 1)
1840 FIELD(V7M_CCR, IC, 17, 1)
1841 FIELD(V7M_CCR, BP, 18, 1)
1842 FIELD(V7M_CCR, LOB, 19, 1)
1843 FIELD(V7M_CCR, TRD, 20, 1)
1846 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1847 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1848 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1849 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1852 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1853 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1854 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1855 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1857 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1858 FIELD(V7M_AIRCR, PRIS, 14, 1)
1859 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1863 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1864 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1865 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1866 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1867 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1868 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1871 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1872 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1873 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1874 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1875 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1876 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1877 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1880 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1881 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1882 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1883 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1884 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1885 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1886 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1894 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1895 FIELD(V7M_HFSR, FORCED, 30, 1)
1896 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1899 FIELD(V7M_DFSR, HALTED, 0, 1)
1900 FIELD(V7M_DFSR, BKPT, 1, 1)
1901 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1902 FIELD(V7M_DFSR, VCATCH, 3, 1)
1903 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1906 FIELD(V7M_SFSR, INVEP, 0, 1)
1907 FIELD(V7M_SFSR, INVIS, 1, 1)
1908 FIELD(V7M_SFSR, INVER, 2, 1)
1909 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1910 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1911 FIELD(V7M_SFSR, LSPERR, 5, 1)
1912 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1913 FIELD(V7M_SFSR, LSERR, 7, 1)
1916 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1917 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1918 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1927 FIELD(V7M_CSSELR, IND, 0, 1)
1928 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1936 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1937 FIELD(V7M_FPCCR, USER, 1, 1)
1938 FIELD(V7M_FPCCR, S, 2, 1)
1939 FIELD(V7M_FPCCR, THREAD, 3, 1)
1940 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1941 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1942 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1943 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1944 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1945 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1946 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1948 FIELD(V7M_FPCCR, TS, 26, 1)
1949 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1950 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1951 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1952 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1953 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1999 FIELD(CTR_EL0, IDC, 28, 1)
2000 FIELD(CTR_EL0, DIC, 29, 1)
2312 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2313 FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
2314 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2315 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2317 FIELD(ID_AA64SMFR0, F16F16, 42, 1)
2318 FIELD(ID_AA64SMFR0, B16B16, 43, 1)
2320 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2323 FIELD(ID_AA64SMFR0, FA64, 63, 1)
2337 FIELD(DBGDIDR, SE_IMP, 12, 1)
2338 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2383 FIELD(GPCCR, GPC, 16, 1)
2384 FIELD(GPCCR, GPCP, 17, 1)
2388 FIELD(MFAR, NSE, 62, 1)
2389 FIELD(MFAR, NS, 63, 1)
2417 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2435 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2438 * if the board doesn't set a value, instead of 1GHz. It is for backwards
2448 return (env->features & (1ULL << feature)) != 0; in arm_feature()
2461 ARMSS_NonSecure = 1,
2625 return 1; in arm_highest_el()
2683 * + NonSecure EL1 & 0 stage 1
2686 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2687 * + Secure EL1 & 0 stage 1
2691 * + Realm EL1 & 0 stage 1 (FEAT_RME)
2696 * + NonSecure PL1 & 0 stage 1
2703 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2706 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2711 * handling via the TLB. The only way to do a stage 1 translation without
2715 * lookup or when loading the descriptors during a stage 1 page table walk,
2734 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
2735 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
2736 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
2805 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2824 /* TLBs with 1-1 mapping to the physical address spaces. */
2835 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2856 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2889 ARMASIdx_S = 1,
2929 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
2956 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
2957 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
2958 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
2959 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
2964 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
2965 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
2966 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
2967 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
2973 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
2987 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
2988 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
2989 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
2995 FIELD(TBFLAG_A32, NS, 10, 1)
3000 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3006 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3008 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3010 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
3012 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
3014 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
3016 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
3018 FIELD(TBFLAG_M32, SECURE, 6, 1)
3027 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3028 FIELD(TBFLAG_A64, BT, 9, 1)
3031 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3032 FIELD(TBFLAG_A64, ATA, 15, 1)
3034 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3035 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3037 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3038 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3041 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3042 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1)
3043 FIELD(TBFLAG_A64, NAA, 30, 1)
3044 FIELD(TBFLAG_A64, ATA0, 31, 1)
3045 FIELD(TBFLAG_A64, NV, 32, 1)
3046 FIELD(TBFLAG_A64, NV1, 33, 1)
3047 FIELD(TBFLAG_A64, NV2, 34, 1)
3049 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1)
3051 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
3052 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */
3053 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */
3085 return EX_TBFLAG_A64(env->hflags, VL) + 1; in sve_vq()
3096 return EX_TBFLAG_A64(env->hflags, SVL) + 1; in sme_vq()
3102 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. in bswap_code()
3103 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 in bswap_code()
3117 QEMU_PSCI_CONDUIT_SMC = 1,
3175 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg()
3210 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)