hw/sd/sdhci-internal.h

54 #define SDHC_CMD_DATA_PRESENT          (1 << 5)
55 #define SDHC_CMD_SUSPEND               (1 << 6)
56 #define SDHC_CMD_RESUME                (1 << 7)
57 #define SDHC_CMD_ABORT                 ((1 << 6)|(1 << 7))
58 #define SDHC_CMD_TYPE_MASK             ((1 << 6)|(1 << 7))
63 /* ROC Response Register 1 0x0 */
87 FIELD(SDHC_PRNSTS, CMD_LVL,            24, 1);
109 #define SDHC_POWER_ON                  (1 << 0)
110 FIELD(SDHC_PWRCON, BUS_VOLTAGE,        1, 3);
119 #define SDHC_WKUP_ON_INS               (1 << 1)
120 #define SDHC_WKUP_ON_RMV               (1 << 2)
126 #define SDHC_CLOCK_SDCLK_EN            (1 << 2)
182 #define SDHC_NORINTSIG_INSERT          (1 << 6)
183 #define SDHC_NORINTSIG_REMOVE          (1 << 7)
190 FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR,  1, 1);
191 FIELD(SDHC_ACMD12ERRSTS, CRC_ERR,      2, 1);
192 FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR,    4, 1);
197 FIELD(SDHC_HOSTCTL2, V18_ENA,          3, 1); /* UHS-I only */
199 FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING,   6, 1); /* UHS-I only */
200 FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL,  7, 1); /* UHS-I only */
201 FIELD(SDHC_HOSTCTL2, UHS_II_ENA,       8, 1); /* since v4 */
202 FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH,    10, 1); /* since v4 */
203 FIELD(SDHC_HOSTCTL2, CMD23_ENA,       11, 1); /* since v4 */
204 FIELD(SDHC_HOSTCTL2, VERSION4,        12, 1); /* since v4 */
205 FIELD(SDHC_HOSTCTL2, ASYNC_INT,       14, 1);
206 FIELD(SDHC_HOSTCTL2, PRESET_ENA,      15, 1);
211 FIELD(SDHC_CAPAB, TOUNIT,              7, 1);
214 FIELD(SDHC_CAPAB, EMBEDDED_8BIT,      18, 1); /* since v3 */
215 FIELD(SDHC_CAPAB, ADMA2,              19, 1); /* since v2 */
216 FIELD(SDHC_CAPAB, ADMA1,              20, 1); /* v1 only? */
217 FIELD(SDHC_CAPAB, HIGHSPEED,          21, 1);
218 FIELD(SDHC_CAPAB, SDMA,               22, 1);
219 FIELD(SDHC_CAPAB, SUSPRESUME,         23, 1);
220 FIELD(SDHC_CAPAB, V33,                24, 1);
221 FIELD(SDHC_CAPAB, V30,                25, 1);
222 FIELD(SDHC_CAPAB, V18,                26, 1);
223 FIELD(SDHC_CAPAB, BUS64BIT_V4,        27, 1); /* since v4.10 */
224 FIELD(SDHC_CAPAB, BUS64BIT,           28, 1); /* since v2 */
225 FIELD(SDHC_CAPAB, ASYNC_INT,          29, 1); /* since v3 */
230 FIELD(SDHC_CAPAB, DRIVER_TYPE_A,      36, 1); /* since v3 */
231 FIELD(SDHC_CAPAB, DRIVER_TYPE_C,      37, 1); /* since v3 */
232 FIELD(SDHC_CAPAB, DRIVER_TYPE_D,      38, 1); /* since v3 */
234 FIELD(SDHC_CAPAB, SDR50_TUNING,       45, 1); /* since v3 */
237 FIELD(SDHC_CAPAB, ADMA3,              59, 1); /* since v4.20 */
238 FIELD(SDHC_CAPAB, V18_VDD2,           60, 1); /* since v4.20 */
254 #define SDHC_ADMAERR_LENGTH_MISMATCH   (1 << 2)
256 #define SDHC_ADMAERR_STATE_ST_FDS      (1 << 0)
262 #define SDHC_ADMA_ATTR_SET_LEN         (1 << 4)
263 #define SDHC_ADMA_ATTR_ACT_TRAN        (1 << 5)
265 #define SDHC_ADMA_ATTR_INT             (1 << 2)
266 #define SDHC_ADMA_ATTR_END             (1 << 1)
267 #define SDHC_ADMA_ATTR_VALID           (1 << 0)
268 #define SDHC_ADMA_ATTR_ACT_MASK        ((1 << 4)|(1 << 5))
285     sdhc_gap_read   = 1,  /* SDHC stopped at block gap during read operation */