Lines Matching full:1
144 /* BAR 1 */
161 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
166 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
173 #define VMXNET3_IO_TYPE_VD 1
206 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
211 * Byte 1 : rsvd gen 13.len.8
217 * Byte 1 : 5.msscof.0 ext1 dtype
233 u32 ext1:1;
234 u32 dtype:1; /* descriptor type */
235 u32 rsvd:1;
236 u32 gen:1; /* generation bit */
240 u32 gen:1; /* generation bit */
241 u32 rsvd:1;
242 u32 dtype:1; /* descriptor type */
243 u32 ext1:1;
254 u32 ti:1; /* VLAN Tag Insertion */
255 u32 ext2:1;
256 u32 cq:1; /* completion request */
257 u32 eop:1; /* End Of Packet */
263 u32 eop:1; /* End Of Packet */
264 u32 cq:1; /* completion request */
265 u32 ext2:1;
266 u32 ti:1; /* VLAN Tag Insertion */
286 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
287 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
288 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
298 #define VMXNET3_TCD_GEN_SIZE 1
322 u32 gen:1; /* generation bit */
328 u32 gen:1; /* generation bit */
340 u32 gen:1; /* Generation bit */
342 u32 dtype:1; /* Descriptor type */
343 u32 btype:1; /* Buffer Type */
347 u32 btype:1; /* Buffer Type */
348 u32 dtype:1; /* Descriptor type */
350 u32 gen:1; /* Generation bit */
360 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
370 u32 ext2:1;
371 u32 cnc:1; /* Checksum Not Calculated */
374 u32 sop:1; /* Start of Packet */
375 u32 eop:1; /* End of Packet */
381 u32 eop:1; /* End of Packet */
382 u32 sop:1; /* Start of Packet */
385 u32 cnc:1; /* Checksum Not Calculated */
386 u32 ext2:1;
398 u32 ts:1; /* Tag is stripped */
399 u32 err:1; /* Error */
403 u32 err:1; /* Error */
404 u32 ts:1; /* Tag is stripped */
414 u32 gen:1; /* generation bit */
416 u32 fcs:1; /* Frame CRC correct */
417 u32 frg:1; /* IP Fragment */
418 u32 v4:1; /* IPv4 */
419 u32 v6:1; /* IPv6 */
420 u32 ipc:1; /* IP Checksum Correct */
421 u32 tcp:1; /* TCP packet */
422 u32 udp:1; /* UDP packet */
423 u32 tuc:1; /* TCP/UDP Checksum Correct */
427 u32 tuc:1; /* TCP/UDP Checksum Correct */
428 u32 udp:1; /* UDP packet */
429 u32 tcp:1; /* TCP packet */
430 u32 ipc:1; /* IP Checksum Correct */
431 u32 v6:1; /* IPv6 */
432 u32 v4:1; /* IPv4 */
433 u32 frg:1; /* IP Fragment */
434 u32 fcs:1; /* Frame CRC correct */
436 u32 gen:1; /* generation bit */
447 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
452 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
453 1 << VMXNET3_RCD_IPC_SHIFT)
454 #define VMXNET3_TXD_GEN_SIZE 1
455 #define VMXNET3_TXD_EOP_SIZE 1
460 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
478 #define VMXNET3_INIT_GEN 1
481 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
484 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
491 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
498 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
502 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
529 VMXNET3_GOS_BITS_32 = 1,
534 #define VMXNET3_GOS_TYPE_LINUX 1
618 VMXNET3_IMM_ACTIVE = 1,
624 VMXNET3_IT_INTX = 1,
631 /* addition 1 for events */
764 #define VMXNET3_ECR_RQERR (1 << 0)
765 #define VMXNET3_ECR_TQERR (1 << 1)
766 #define VMXNET3_ECR_LINK (1 << 2)
767 #define VMXNET3_ECR_DIC (1 << 3)
768 #define VMXNET3_ECR_DEBUG (1 << 4)
783 (vfTable[vid >> 5] |= (1 << (vid & 31)))
785 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
788 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
793 #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */