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/qemu/hw/arm/
H A Dbcm2838.c6 * SPDX-License-Identifier: GPL-2.0-or-later
25 /* Number of external interrupt lines to configure the GIC with */
28 #define PPI(cpu, irq) (GIC_NUM_IRQS + (cpu) * GIC_INTERNAL + GIC_NR_SGIS + irq) argument
34 #define GIC_VIFACE_OTHER_OFS(cpu) (0x5000 + (cpu) * 0x200) argument
44 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in bcm2838_gic_set_irq()
51 object_initialize_child(obj, "peripherals", &s->peripherals, in bcm2838_init()
53 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), in bcm2838_init()
54 "board-rev"); in bcm2838_init()
55 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), in bcm2838_init()
56 "vcram-size"); in bcm2838_init()
[all …]
H A Dbcm2836.c9 * See the COPYING file in the top-level directory.
18 #include "target/arm/cpu-qom.h"
22 DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);
30 for (n = 0; n < bc->core_count; n++) { in bcm283x_base_init()
31 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, in bcm283x_base_init()
32 bc->cpu_type); in bcm283x_base_init()
34 if (bc->core_count > 1) { in bcm283x_base_init()
36 qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); in bcm283x_base_init()
39 if (bc->ctrl_base) { in bcm283x_base_init()
40 object_initialize_child(obj, "control", &s->control, in bcm283x_base_init()
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H A Dvexpress.c4 * Copyright (c) 2010 - 2011 B Labs Ltd.
20 * Contributions after 2012-01-13 are licensed under the terms of the
38 #include "qemu/error-report.h"
41 #include "hw/cpu/a9mpcore.h"
42 #include "hw/cpu/a15mpcore.h"
48 #include "target/arm/cpu-qom.h"
63 * the "legacy" one (used for A9) and the "Cortex-A Series"
189 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
190 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
218 unsigned int smp_cpus = ms->smp.cpus; in init_cpus()
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H A Dversatilepb.c4 * Copyright (c) 2005-2007 CodeSourcery.
24 #include "qemu/error-report.h"
29 #include "target/arm/cpu-qom.h"
36 /* Primary interrupt controller. */
68 flags = s->level & s->mask; in vpb_sic_update()
69 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
79 if (!(s->pic_enable & mask)) in vpb_sic_update_pic()
81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
89 s->level |= 1u << irq; in vpb_sic_set_irq()
91 s->level &= ~(1u << irq); in vpb_sic_set_irq()
[all …]
/qemu/docs/specs/
H A Dppc-xive.rst2 POWER9 XIVE interrupt controller
5 The POWER9 processor comes with a new interrupt controller
6 architecture, called XIVE as "eXternal Interrupt Virtualization
10 XIVE are to support a larger number of interrupt sources and to
19 The XIVE IC is composed of three sub-engines, each taking care of a
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
24 Interface (PSI) host bridge Controller, but also inside the main
25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
29 Controller (VC). It handles event coalescing and perform interrupt
[all …]
H A Dppc-spapr-xive.rst4 The POWER9 processor comes with a new interrupt controller
5 architecture, called XIVE as "eXternal Interrupt Virtualization
6 Engine". It supports a larger number of interrupt sources and offers
11 processors can run under two interrupt modes:
13 - *Legacy Compatibility Mode*
20 - *XIVE native exploitation mode*
23 structures, and provides direct control for interrupt management
26 Which interrupt modes can be used by the machine is negotiated with
30 Both interrupt mode share the same IRQ number space. See below for the
34 ---------------
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H A Driscv-aia.rst1 .. _riscv-aia:
3 RISC-V AIA support for RISC-V machines
6 AIA (Advanced Interrupt Architecture) support is implemented in the ``virt``
7 RISC-V machine for TCG and KVM accelerators.
11 - "aia=aplic": adds one or more APLIC (Advanced Platform Level Interrupt Controller)
13 - "aia=aplic-imsic": adds one or more APLIC device and an IMSIC (Incoming MSI
14 Controller) device for each CPU
18 emulated in userspace versus what is being emulated by an in-kernel irqchip.
21 (m-mode) APLIC and IMSIC (when applicable).
25 - no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of
[all …]
/qemu/hw/loongarch/
H A Dvirt-fdt-build.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include "qemu/error-report.h"
7 #include "qemu/guest-random.h"
10 #include "hw/core/sysbus-fdt.h"
14 #include "hw/pci-host/gpex.h"
15 #include "hw/pci-host/ls7a.h"
18 #include "target/loongarch/cpu.h"
25 ms->fdt = create_device_tree(&lvms->fdt_size); in create_fdt()
26 if (!ms->fdt) { in create_fdt()
32 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", in create_fdt()
[all …]
/qemu/hw/intc/
H A Dslavio_intctl.c2 * QEMU Sparc SLAVIO interrupt controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
37 * Registers of interrupt controller in sun4m.
39 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
43 * There is a system master controller and one for each cpu.
56 uint32_t cpu; member
88 // per-cpu interrupt controller
98 ret = s->intreg_pending; in slavio_intctl_mem_readl()
104 trace_slavio_intctl_mem_readl(s->cpu, addr, ret); in slavio_intctl_mem_readl()
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H A Dspapr_xive.c2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
24 #include "hw/qdev-properties.h"
28 * XIVE Virtualization Controller BAR and Thread Management BAR that we
38 * controller model does not have the same constraints and can use a
39 * simple mapping scheme of the CPU vcpu_id
51 return nvt_idx - SPAPR_XIVE_NVT_BASE; in spapr_xive_nvt_to_target()
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H A Darm_gicv3.c2 * ARM Generic Interrupt Controller v3 (emulation)
12 /* This file contains implementation code for an interrupt controller
28 * pending interrupt for this CPU. We also return true if in irqbetter()
29 * the current recorded highest priority pending interrupt in irqbetter()
33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
38 * The same priority IRQ with non-maskable property should signal to in irqbetter()
39 * the CPU as it have the priority higher than the labelled 0x80 or 0x00. in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
46 * IMPDEF choice which of them to signal to the CPU. We choose to in irqbetter()
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H A Dspapr_xive_kvm.c2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2019, IBM Corporation.
7 * COPYING file in the top-level directory.
12 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
28 * Helpers for CPU hotplug
46 if (enabled_cpu->vcpu_id == vcpu_id) { in kvm_cpu_is_enabled()
59 enabled_cpu->vcpu_id = vcpu_id; in kvm_cpu_enable()
74 * XIVE Thread Interrupt Management context (KVM)
79 SpaprXive *xive = SPAPR_XIVE(tctx->xptr); in kvmppc_xive_cpu_set_state()
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/qemu/hw/riscv/
H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
39 #include "qemu/error-report.h"
46 #include "hw/cpu/cluster.h"
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H A Dvirt.c2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
36 #include "hw/riscv/riscv-iommu-bits.h"
46 #include "hw/platform-bus.h"
[all …]
/qemu/include/hw/ppc/
H A Dxive.h2 * QEMU PowerPC XIVE interrupt controller model
5 * The POWER9 processor comes with a new interrupt controller, called
6 * XIVE as "eXternal Interrupt Virtualization Engine".
11 * XIVE Interrupt Controller
12 * +------------------------------------+ IPIs
13 * | +---------+ +---------+ +--------+ | +-------+
14 * | |VC | |CQ | |PC |----> | CORES |
15 * | | esb | | | | |----> | |
16 * | | eas | | Bridge | | tctx |----> | |
18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
[all …]
/qemu/docs/system/
H A Dtarget-mips.rst1 .. _MIPS-System-emulator:
4 --------------------
6 Four executables cover simulation of 32 and 64-bit MIPS systems in both
7 endian options, ``qemu-system-mips``, ``qemu-system-mipsel``
8 ``qemu-system-mips64`` and ``qemu-system-mips64el``. Five different
11 - The MIPS Malta prototype board \"malta\"
13 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator.
15 - MIPS emulator pseudo board \"mipssim\"
17 - A MIPS Magnum R4000 machine \"magnum\". This machine needs the
18 64-bit emulator.
[all …]
/qemu/docs/system/arm/
H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
7 AST2500 with an ARM1176JZS CPU (800MHz), the AST2600
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz).
15 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
16 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
17 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
18 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
22 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
23 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
[all …]
H A Dvirt.rst1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
26 migrated, it is recommended to use another cpu model instead.
33 - PCI/PCIe devices
34 - Flash memory
[all …]
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
22 * Interrupt controller
23 * DMA controller
24 * Clock and reset controller (CPRMAN)
[all …]
/qemu/docs/system/ppc/
H A Dppce500.rst8 -----------------
14 * Multicore Programmable Interrupt Controller (MPIC) with MSI support
16 * 1 Freescale MPC8xxx I2C controller
18 * 1 Freescale MPC8xxx GPIO controller
19 * Power-off functionality via one GPIO pin
20 * 1 Freescale MPC8xxx PCI host controller
22 * 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
23 * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
26 ----------------------------------
29 which it passes to the guest, if there is no ``-dtb`` option. This provides
[all …]
/qemu/pc-bios/dtb/
H A Dbamboo.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
30 cpu@0 {
31 device_type = "cpu";
34 clock-frequency = <0x1fca0550>;
35 timebase-frequency = <0x017d7840>;
[all …]
H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
31 cpu@0 {
32 device_type = "cpu";
35 clock-frequency = <0>; /* Filled in by U-Boot */
[all …]
/qemu/include/hw/sd/
H A Dallwinner-sdhost.h2 * Allwinner (sun4i and above) SD Host Controller emulation
32 /** Generic Allwinner SD Host Controller (abstract) */
33 #define TYPE_AW_SDHOST "allwinner-sdhost"
36 #define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
39 #define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
41 /** Allwinner sun50i-a64 */
42 #define TYPE_AW_SDHOST_SUN50I_A64 TYPE_AW_SDHOST "-sun50i-a64"
44 /** Allwinner sun50i-a64 emmc */
45 #define TYPE_AW_SDHOST_SUN50I_A64_EMMC TYPE_AW_SDHOST "-sun50i-a64-emmc"
59 * Allwinner SD Host Controller object instance state.
[all …]
/qemu/include/hw/misc/
H A Dtz-msc.h2 * ARM TrustZone master security controller emulation
13 * This is a model of the TrustZone master security controller (MSC).
14 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
16 * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
19 * a DMA controller) and allows secure software to configure it to either
22 * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
24 * The MSC has no register interface -- it is configured purely by a
26 * they are either hardwired or exposed in an ad-hoc register interface by
38 * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
39 * + Named GPIO output "irq": set for a transaction-failed interrupt
[all …]
/qemu/hw/openrisc/
H A Dvirt.c2 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "qemu/error-report.h"
11 #include "qemu/guest-random.h"
13 #include "cpu.h"
14 #include "system/address-spaces.h"
17 #include "hw/char/serial-mm.h"
18 #include "hw/core/split-irq.h"
22 #include "hw/pci-host/gpex.h"
23 #include "hw/qdev-properties.h"
26 #include "hw/virtio/virtio-mmio.h"
[all …]

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