Lines Matching +full:cpu +full:- +full:interrupt +full:- +full:controller

2  * ARM TrustZone master security controller emulation
13  * This is a model of the TrustZone master security controller (MSC).
14  * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
16  * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
19  * a DMA controller) and allows secure software to configure it to either
22  * behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
24  * The MSC has no register interface -- it is configured purely by a
26  * they are either hardwired or exposed in an ad-hoc register interface by
38  * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
39  * + Named GPIO output "irq": set for a transaction-failed interrupt
43  *   addresses should be treated as secure and which as non-secure.
44  *   This need not be the same IDAU as the one used by the CPU.
57 #define TYPE_TZ_MSC "tz-msc"