#
f0737158 |
| 20-May-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/riscv: clean up supported MMU modes, declarative CPU definitions, remove .instance_post_init (reviewed by Alistair
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/riscv: clean up supported MMU modes, declarative CPU definitions, remove .instance_post_init (reviewed by Alistair) * qom: reverse order of instance_post_init calls * qapi/misc-target: doc and standard improvements for SGX * hw/pci-host/gt64120: Fix endianness handling * i386/hvf: Make CPUID_HT supported * i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmgsLEsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroMosgf+IbsERBx/JTsjv2tKfCdAKXGmZ6xv # JIb6SzXkuA0TBScUm0U1zluimNWHqqnSWQ/ogxhw69rqEkAZiFGbahpt9udD19kN # 7oSLmj64a0a4uJZmWeMQ3rPO8zehg6t5K0sKXyR3d49pghw9NCzWabXdDypaV4VC # sgl9zS46PMjG12XBSq7zwQsUPGwIE6OICtxM/UMgvlqdoI+sZjYU39MpmBf5I0DQ # /VwGnZPc1pVwZqYn5sV075N4bjN+JYlaZN4+OcuRrU5bw4M8ZEwKxL+/b65ilp5S # EqDXuxAilMS/0orC7YpCEf9Dryy/w8n3q4ejV8LQ5K6gnsOFTTurdNlWog== # =bsKR # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 May 2025 03:16:27 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits) qom: reverse order of instance_post_init calls target/riscv: remove .instance_post_init target/riscv: convert Xiangshan Nanhu to RISCVCPUDef target/riscv: convert Ventana V1 to RISCVCPUDef target/riscv: convert TT Ascalon to RISCVCPUDef target/riscv: convert THead C906 to RISCVCPUDef target/riscv: generalize custom CSR functionality target/riscv: th: make CSR insertion test a bit more intuitive target/riscv: convert SiFive U models to RISCVCPUDef target/riscv: convert ibex CPU models to RISCVCPUDef target/riscv: convert SiFive E CPU models to RISCVCPUDef target/riscv: convert dynamic CPU models to RISCVCPUDef target/riscv: convert bare CPU models to RISCVCPUDef target/riscv: convert profile CPU models to RISCVCPUDef target/riscv: convert abstract CPU classes to RISCVCPUDef target/riscv: add more RISCVCPUDef fields target/riscv: include default value in cpu_cfg_fields.h.inc target/riscv: move RISCVCPUConfig fields to a header file target/riscv: merge riscv_cpu_class_init with the class_base function target/riscv: store RISCVCPUDef struct directly in the class ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
211c7f9b |
| 18-Feb-2025 |
Paolo Bonzini <pbonzini@redhat.com> |
target/riscv: update max_satp_mode based on QOM properties
Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properti
target/riscv: update max_satp_mode based on QOM properties
Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properties back into it. For TCG, deduce the bitmap of supported modes from valid_vm[].
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
2af4a82a |
| 19-May-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu into staging
First RISC-V PR for 10.1
* Add support for RIMT to virt machine ACPI * Don't allow PMP RLB to bypass rule
Merge tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu into staging
First RISC-V PR for 10.1
* Add support for RIMT to virt machine ACPI * Don't allow PMP RLB to bypass rule privileges * Fix checks on writes to pmpcfg in Smepmp MML mode * Generate strided vector loads/stores with tcg nodes * Improve Microchip Polarfire SoC customization * Use tcg ops generation to emulate whole reg rvv loads/stores * Expand the probe_pages helper function to handle probe flags * Fix type conflict of GLib function pointers * Fix endless translation loop on big endian systems * Use tail pseudoinstruction for calling tail * Fix some RISC-V vector instruction corner cases * MAINTAINERS: Add common-user/host/riscv to RISC-V section * Fix write_misa vs aligned next_pc * KVM CSR fixes * Virt machine memmap usage cleanup
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmgqreUACgkQr3yVEwxT # gBMurA//WAX4X+aNi6keCr20Ffv3gUnkPPeVewLLKOrZZ7h5oyWtRcSQvwDBSr8C # vzs4Rf492iNljnbRj09KYkLB8Qq/QH2Ixl+IgG8ueJAHJ8WdG6HYrrDxcONwgL1K # lQrRaDrMCFjU35uDlejfuvWWEmb4GKDMfj/wxs5wgNvnHgNhThmVaWQysx8KHYU+ # tevPQj5s4mvVGztGRSHIZQ8bth7oVUQR5CsKngGEmVLS2L6yVYTUN5ZhB5g6Ikrq # jKn44cROLfvv+0zPB9Lgu7eKauA/h8SckjCV+dGoMDB5J5M/TvwS118VHOjNVEQZ # yLx6/BdLp3SRPwbvu9jn6vjms95iZSJXXdnY+Cg4MqAbuIRQK66n6Zoa3LjbEk2U # zsf03uYUla9CBs6VQJmF7yjks3AbWokpZ9WSsGIcHJgXe8pEUeEsWOgiBhifJ5bD # Hljlkiw1gHCjhtc2aWEH0aBwM7896lmdct70JmkjQ4uZKkFSqJ8y5l0Gm3lvgvdO # OEPyMbZ6hSO4UZovcpeFtOoXteCUVthvqz0mADoQAtG+2qoX0k+9h8v305fhlti+ # bXJfu1QPsQqCYMrv4ZSTbRg0uC8m7CHnA+coC0XnCcMwEk9ZBl373/cnQYWsmqo8 # lxZmXLvpaN9CEzjOmZhXUsOvIqAJdM1sYPWnoXJ71t7mn4QEOPA= # =dFjk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 May 2025 00:04:53 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu: (56 commits) hw/riscv/virt.c: remove 'long' casts in fmt strings hw/riscv/virt.c: use s->memmap in finalize_fdt() functions hw/riscv/virt.c: use s->memmap in create_fdt_virtio() hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path hw/riscv/virt.c: use s->memmap in create_fdt() path hw/riscv/virt.c: add 'base' arg in create_fw_cfg() hw/riscv/virt.c: use s->memmap in virt_machine_done() hw/riscv/virt.c: remove trivial virt_memmap references hw/riscv/virt.c: enforce s->memmap use in machine_init() target/riscv/kvm: add scounteren CSR target/riscv/kvm: read/write KVM regs via env size target/riscv/kvm: add senvcfg CSR target/riscv/kvm: do not read unavailable CSRs target/riscv/kvm: add kvm_csr_cfgs[] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro target/riscv/kvm: turn u32/u64 reg functions into macros target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg() target/riscv/kvm: minor fixes/tweaks target/riscv: Fix write_misa vs aligned next_pc target/riscv: Move insn_len to internals.h ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
e7cb99bf |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: remove 'long' casts in fmt strings
We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt strings for uint64_t and hwaddr types.
Signed-off-by: Daniel Henrique Ba
hw/riscv/virt.c: remove 'long' casts in fmt strings
We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt strings for uint64_t and hwaddr types.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
621e4527 |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and create_fdt_rtc() to use s->memmap in their logic.
Signed-off-by: Danie
hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and create_fdt_rtc() to use s->memmap in their logic.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
a51a88fd |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
create_fdt_virtio() can use s->memmap instead of having an extra argument for it.
While we're at it rewrite it a little bit to avoid the clunky
hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
create_fdt_virtio() can use s->memmap instead of having an extra argument for it.
While we're at it rewrite it a little bit to avoid the clunky line in 'name' and code repetition:
- declare 'virtio_base' out of the loop since it never changes; - declare a 'size' variable. Use it to calculate the address of the virtio device in an 'addr' variable; - use 'addr' in the 'name' g_strdup_printf(); - use 'addr' and 'size' when creating the 'reg' property.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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04c4f8d1 |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
create_fdt_sockets() and all its fdt helpers (create_fdt_socket_aplic(), create_fdt_imsic(), create_fdt_socket_plic(), create_fdt_socket_a
hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
create_fdt_sockets() and all its fdt helpers (create_fdt_socket_aplic(), create_fdt_imsic(), create_fdt_socket_plic(), create_fdt_socket_aclint() and create_fdt_socket_memory()) can use s->memmap from their RISCVVirtState pointer instead of having an extra memmap argument.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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658e5019 |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: use s->memmap in create_fdt() path
create_fdt(), create_fdt_flash() and create_fdt_fw_cfg() can access the memmap via their RISCVVirtState pointers.
Signed-off-by: Daniel Henrique
hw/riscv/virt.c: use s->memmap in create_fdt() path
create_fdt(), create_fdt_flash() and create_fdt_fw_cfg() can access the memmap via their RISCVVirtState pointers.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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6418ff38 |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
The function can receive the value via s->memmap[VIRT_FW_CFG].base from the caller, avoiding the use of virt_memmap.
Signed-off-by: Daniel Henriqu
hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
The function can receive the value via s->memmap[VIRT_FW_CFG].base from the caller, avoiding the use of virt_memmap.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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47e51e5d |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: use s->memmap in virt_machine_done()
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <2025042
hw/riscv/virt.c: use s->memmap in virt_machine_done()
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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fb8cf3fd |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: remove trivial virt_memmap references
We should use s->memmap instead of virt_memmap to be able to use an updated memmap when we start versioning the board.
Signed-off-by: Daniel H
hw/riscv/virt.c: remove trivial virt_memmap references
We should use s->memmap instead of virt_memmap to be able to use an updated memmap when we start versioning the board.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250429125811.224803-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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221e96cb |
| 29-Apr-2025 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
hw/riscv/virt.c: enforce s->memmap use in machine_init()
Throughout the code we're accessing the board memmap, most of the time, by accessing it statically via 'virt_memmap'. This static map is also
hw/riscv/virt.c: enforce s->memmap use in machine_init()
Throughout the code we're accessing the board memmap, most of the time, by accessing it statically via 'virt_memmap'. This static map is also assigned in the machine state in s->memmap.
We're also passing it as a variable to some fdt functions, which is unorthodox since we can spare a function argument by accessing it statically or via the machine state.
All the current forms are valid but not all of the are scalable. In the future we will version this board, and then all this code will need rework because it should point to the updated memmap. In this case, we'll want to assign the adequate versioned memmap once during init, in s->memmap like it is being done today, and the rest of the code will access the updated map via s->memmap.
We're also enforcing the pattern of using s->memmap instead of assigning it to a temp variable 'memmap'. Code is copy/pasted around all the time and being consistent is important.
We'll start these rather mechanical changes with virt_machine_init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-ID: <20250429125811.224803-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
d2a88aca |
| 22-Mar-2025 |
Sunil V L <sunilvl@ventanamicro.com> |
hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure
When the IOMMU is implemented as a PCI device, its BDF is created locally in virt.c. However, the same BDF is also required in virt-ac
hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure
When the IOMMU is implemented as a PCI device, its BDF is created locally in virt.c. However, the same BDF is also required in virt-acpi-build.c to support ACPI. Therefore, make this information part of the global RISCVVirtState structure so that it can be accessed outside of virt.c as well.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250322043139.2003479-2-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
06b40d25 |
| 27-Apr-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'single-binary-20250425' of https://github.com/philmd/qemu into staging
Various patches loosely related to single binary work:
- Replace cpu_list() definition by CPUClass::list_cpus() cal
Merge tag 'single-binary-20250425' of https://github.com/philmd/qemu into staging
Various patches loosely related to single binary work:
- Replace cpu_list() definition by CPUClass::list_cpus() callback - Remove few MO_TE definitions on Hexagon / X86 targets - Remove target_ulong uses in ARMMMUFaultInfo and ARM CPUWatchpoint - Remove DEVICE_HOST_ENDIAN definition - Evaluate TARGET_BIG_ENDIAN at compile time and use target_needs_bswap() more - Rename target_words_bigendian() as target_big_endian() - Convert target_name() and target_cpu_type() to TargetInfo API - Constify QOM TypeInfo class_data/interfaces fields - Get default_cpu_type calling machine_class_default_cpu_type() - Correct various uses of GLibCompareDataFunc prototype - Simplify ARM/Aarch64 gdb_get_core_xml_file() handling a bit - Move device tree files in their own pc-bios/dtb/ subdir - Correctly check strchrnul() symbol availability on macOS SDK - Move target-agnostic methods out of cpu-target.c and accel-target.c - Unmap canceled USB XHCI packet - Use deposit/extract API in designware model - Fix MIPS16e translation - Few missing header fixes
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmgLqb8ACgkQ4+MsLN6t # wN6nCQ//cmv1M+NsndhO5TAK8T1eUSXKlTZh932uro6ZgxKwN4p+j1Qo7bq3O9gu # qUMHNbcfQl8sHSytiXBoxCjLMCXC3u38iyz75WGXuPay06rs4wqmahqxL4tyno3l # 1RviFts9xlLn+tJqqrAR6+pRdALld0TY+yXUjXgr4aK5pIRpLz9U/sIEoh7qbA5U # x0MTaceDG3A91OYo0TgrNbcMe1b9GqQZ+a4tbaP+oE37wbiKdyQ68LjrEbV08Y1O # qrFF4oxquV31QJcUiuII1W7hC6psGrMsUA1f1qDu7QvmybAZWNZNsR9T66X9jH5J # wXMShJmmXwxugohmuPPFnDshzJy90aFL6Jy2shrfqcG2v0W66ARY1ZnbJLCcfczt # 073bnE2dnOVhd/ny37RrIJNJLLmYM0yFDeKuYtNNAzpK9fpA7Q2PI8QiqNacQ3Pa # TdEYrGlMk7OeNck8xJmJMY5rATthi1D4dIBv3rjQbUolQvPJe2Y9or0R2WL1jK5v # hhr6DY01iSPES3CravmUs/aB1HRMPi/nX45OmFR6frAB7xqWMreh81heBVuoTTK8 # PuXtRQgRMRKwDeTxlc6p+zba4mIEYG8rqJtPFRgViNCJ1KsgSIowup3BNU05YuFn # NoPoRayMDVMgejVgJin3Mg2DCYvt/+MBmO4IoggWlFsXj59uUgA= # =DXnZ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 25 Apr 2025 11:26:55 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'single-binary-20250425' of https://github.com/philmd/qemu: (58 commits) qemu: Convert target_name() to TargetInfo API accel: Move target-agnostic code from accel-target.c -> accel-common.c accel: Make AccelCPUClass structure target-agnostic accel: Include missing 'qemu/accel.h' header in accel-internal.h accel: Implement accel_init_ops_interfaces() for both system/user mode cpus: Move target-agnostic methods out of cpu-target.c cpus: Replace CPU_RESOLVING_TYPE -> target_cpu_type() qemu: Introduce target_cpu_type() qapi: Rename TargetInfo structure as QemuTargetInfo hw/microblaze: Evaluate TARGET_BIG_ENDIAN at compile time hw/mips: Evaluate TARGET_BIG_ENDIAN at compile time target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile time target/mips: Check CPU endianness at runtime using env_is_bigendian() accel/kvm: Use target_needs_bswap() linux-user/elfload: Use target_needs_bswap() target/hexagon: Include missing 'accel/tcg/getpc.h' accel/tcg: Correct list of included headers in tcg-stub.c system/kvm: make functions accessible from common code meson: Use osdep_prefix for strchrnul() meson: Share common C source prefixes ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
2cd09e47 |
| 23-Apr-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
qom: Make InterfaceInfo[] uses const
Mechanical change using:
$ sed -i -E 's/\(InterfaceInfo.?\[/\(const InterfaceInfo\[/g' \ $(git grep -lE '\(InterfaceInfo.?\[\]\)')
Reviewed-by:
qom: Make InterfaceInfo[] uses const
Mechanical change using:
$ sed -i -E 's/\(InterfaceInfo.?\[/\(const InterfaceInfo\[/g' \ $(git grep -lE '\(InterfaceInfo.?\[\]\)')
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250424194905.82506-7-philmd@linaro.org>
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#
12d1a768 |
| 09-Feb-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
qom: Have class_init() take a const data argument
Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script.
Suggested-by: Richard Henderson <richard.henderson@linaro.o
qom: Have class_init() take a const data argument
Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>
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#
019fbfa4 |
| 24-Apr-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into staging
Miscellaneous patches for 2025-04-24
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Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into staging
Miscellaneous patches for 2025-04-24
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* tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru: cleanup: Drop pointless label at end of function cleanup: Drop pointless return at end of function cleanup: Re-run return_directly.cocci
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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720a0e41 |
| 07-Apr-2025 |
Markus Armbruster <armbru@redhat.com> |
cleanup: Re-run return_directly.cocci
Coccinelle's indentation of virt_create_plic() results in a long line. Avoid that by mimicking the old indentation manually.
Don't touch tests/tcg/mips/user/.
cleanup: Re-run return_directly.cocci
Coccinelle's indentation of virt_create_plic() results in a long line. Avoid that by mimicking the old indentation manually.
Don't touch tests/tcg/mips/user/. I'm not sure these files are ours to make style cleanups on. They might be imported third-party code, which we should leave as is to not complicate future updates.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250407082643.2310002-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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c1fc2dd7 |
| 23-Mar-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'uefi-20250321-pull-request' of https://gitlab.com/kraxel/qemu into staging
hw/uefi-vars: bug fixes hw/uefi-vars: support riscv and loongarch docs: update firmware.json spec
# -----BEGIN
Merge tag 'uefi-20250321-pull-request' of https://gitlab.com/kraxel/qemu into staging
hw/uefi-vars: bug fixes hw/uefi-vars: support riscv and loongarch docs: update firmware.json spec
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmfdXR0ACgkQTLbY7tPo # cThurBAA2xXMSS5HxU+8kAgkQQ5UC0c9cSQj//HJB5dAmsZ/I8WEgwv1+XLGnjf0 # SOpAiR0PshTipXdtcUVGpqufAghy+8WkAoYplMqY40o/Bsv8egQzb4XvNPSxqvon # dTDmScn2ns1mtSOOY8LWSFIXFDlYK0uKyXcHSKvw/HNjYsVOb22IAokznyh9eZa0 # OwjhUc9oqTR0s8MrZbu+tKqEfoqGRMIDYVKk1vzjAigw6jfgvaUZ0dtldcwTktsH # w7SyMowUJnNcjnzZxqchj94377feS4OG/QKO7LpnhfdYYHf7CT1BC72xG1Ivloma # A3xK/AnFqbzYuwL3Mtmuk5xV5s98dP/dWvxTc7kZFT++fJ4bljnRhcyqckvWwHD5 # jYjm8ssAn2ukuVDM+O7+tRNMcyBXYc1pgmQCa10XjT0Ds0WulIynITwoguolvCPv # rH/ILe8N2vXa7xxB7DledPMzX74+SWXaHv4n+SKEHoVlSiaP3M85ZNcSYjXf9P37 # hrMyUWgjO0AXJ2aDaCSn9nLJT8jRMcYh9HN03Y7KmyT0SZnksbHvPLF0kB1zFNfa # NBQZUhZacu7iZoNpHx3uT+D1z9GM16S2skkxvryMrS/05iM6amc2kCJPxOp2vbYc # eiyihjFHtW/dfhRmOG92EJ1FRMLx/dB/dBG90oGmTyHMlev6tEQ= # =VN7r # -----END PGP SIGNATURE----- # gpg: Signature made Fri 21 Mar 2025 08:35:41 EDT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* tag 'uefi-20250321-pull-request' of https://gitlab.com/kraxel/qemu: docs/firmware: add feature flag for host uefi variable store hw/uefi-vars-sysbus: allow for loongarch virt hw/uefi-vars-sysbus: allow for riscv virt hw/uefi: fix error handling in uefi_vars_json_load hw/uefi: fix error handling in uefi_vars_json_save hw/uefi: flush variable store to disk in post load
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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5807508f |
| 19-Mar-2025 |
Gerd Hoffmann <kraxel@redhat.com> |
hw/uefi-vars-sysbus: allow for riscv virt
Allow the device being added to riscv virt VMs.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Daniel P. Berrangé <berrange@
hw/uefi-vars-sysbus: allow for riscv virt
Allow the device being added to riscv virt VMs.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20250319141159.1461621-5-kraxel@redhat.com>
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#
9ee72780 |
| 05-Mar-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-riscv-to-apply-20250305-1' of https://github.com/alistair23/qemu into staging
Third RISC-V PR for 10.0
* CSR coverity fixes * Fix unexpected behavior of vector reduction instruction
Merge tag 'pull-riscv-to-apply-20250305-1' of https://github.com/alistair23/qemu into staging
Third RISC-V PR for 10.0
* CSR coverity fixes * Fix unexpected behavior of vector reduction instructions when vl is 0 * Fix incorrect vlen comparison in prop_vlen_set * Throw debug exception before page fault * Remove redundant "hart_idx" masking from APLIC * Add support for Control Transfer Records Ext * Remove redundant struct members from the IOMMU * Remove duplicate definitions from the IOMMU * Fix tick_offset migration for Goldfish RTC * Add serial alias in virt machine DTB * Remove Bin Meng from RISC-V maintainers * Add support for Control Transfer Records Ext * Log guest errors when reserved bits are set in PTEs * Add missing Sdtrig disas CSRs * Correct the hpmevent sscofpmf mask * Mask upper sscofpmf bits during validation * Remove warnings about Smdbltrp/Smrnmi being disabled * Respect mseccfg.RLB bit for TOR mode PMP entry * Update KVM support to Linux 6.14-rc3 * IOMMU HPM support * Support Sscofpmf/Svade/Svadu/Smnpm/Ssnpm extensions in KVM * Add --ignore-family option to binfmt * Refinement for AIA with KVM acceleration * Reset time changes for KVM
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfHrkEACgkQr3yVEwxT # gBNGTA/+N9nBPZt5cv0E/0EDZMQS8RQrQvz1yHRgAXOq8RnOdcL72v8wovGAfnVu # l0BXDoVBvw4f2Xm9Q4ptlfH8HAefCeQ4E/K9j5Lwxr8OqZHFg6e+JQIyZOt6wBWI # hJbz1/laJIbXq3cGgwcE/l0aGfb2UAAsA4dsZVt/MnjAV8GS7BF9RCkgCPxD4FZA # 0PLiq9dF+4o4q7PxnxAbUVz/uhLzqmcnQemQFHbf9Wms3tZEDKmPSoKP/v+01Rkw # tm+cgy7OocpgygbMc0nykYG50P+raUBSesk/jFGeKj8cU4IeMuzDsVPWcd4rG+0X # Z+nENfOY7vOqMCXgaQCW2r4vEQx2Gj0yQG6xmVAemRWzFHJdz5W01/uUSHzJSB+L # +VbAH55HYKr6sbgecqInQ/rsHKyw6D5QFcj/guz+kvhsH9rJ5q60uywrWL5OEuaK # vKv7cSZghlf9bwy6soassXxk8z+j4psJ7WnnVpynNKMew9yFFDhayuIFbo9952gH # 3+NCm2cQrkTYJOXAJwkxBD+I4AXxNSuxNjaVANk9q80uqbT9JiHM7pcvbJI00Fji # OutJSPYtVXEin9Ev3sJ05YQHsIcZ/Noi3O5IdaRI0AMk/8gyGyhFCVgSpV52dH59 # HguPK05e5cW/xgElGUPHrU+UtzE05p18HnSoVPclF/B5rc8QXN0= # =dobk # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 09:52:01 HKT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250305-1' of https://github.com/alistair23/qemu: (59 commits) target/riscv/kvm: add missing KVM CSRs target/riscv/kvm: add kvm_riscv_reset_regs_csr() target/riscv/cpu: remove unneeded !kvm_enabled() check hw/intc/aplic: refine kvm_msicfgaddr hw/intc/aplic: refine the APLIC realize hw/intc/imsic: refine the IMSIC realize binfmt: Add --ignore-family option binfmt: Normalize host CPU architecture binfmt: Shuffle things around target/riscv/kvm: Add some exts support docs/specs/riscv-iommu.rst: add HPM support info hw/riscv: add IOMMU HPM trace events hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap hw/riscv/riscv-iommu: add hpm events mmio write hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes hw/riscv/riscv-iommu: instantiate hpm_timer hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() hw/riscv/riscv-iommu: add riscv-iommu-hpm file hw/riscv/riscv-iommu-bits.h: HPM bits ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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f7345678 |
| 16-Jan-2025 |
Vasilis Liaskovitis <vliaskovitis@suse.com> |
hw/riscv/virt: Add serial alias in DTB
Add an "aliases" node with a "serial0" entry for the single UART in the riscv virt machine.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2774 Signe
hw/riscv/virt: Add serial alias in DTB
Add an "aliases" node with a "serial0" entry for the single UART in the riscv virt machine.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2774 Signed-off-by: Vasilis Liaskovitis <vliaskovitis@suse.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250116161007.39710-1-vliaskovitis@suse.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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b5d5edc1 |
| 04-Feb-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/riscv: Remove all invalid uses of auto_create_sdcard=true
MachineClass::auto_create_sdcard is only useful to automatically create a SD card, attach a IF_SD block drive to it and plug the card ont
hw/riscv: Remove all invalid uses of auto_create_sdcard=true
MachineClass::auto_create_sdcard is only useful to automatically create a SD card, attach a IF_SD block drive to it and plug the card onto a SD bus. None of the RISCV machines modified by this commit try to use the IF_SD interface.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-7-philmd@linaro.org>
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cdc8d7ca |
| 25-Nov-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/boards: Rename no_sdcard -> auto_create_sdcard
Invert the 'no_sdcard' logic, renaming it as the more explicit "auto_create_sdcard". Machines are supposed to create a SD Card drive when this flag
hw/boards: Rename no_sdcard -> auto_create_sdcard
Invert the 'no_sdcard' logic, renaming it as the more explicit "auto_create_sdcard". Machines are supposed to create a SD Card drive when this flag is set. In many cases it doesn't make much sense (as boards don't expose SD Card host controller), but this is patch only aims to expose that nonsense; so no logical change intended (mechanical patch using gsed).
Most of the changes are:
- mc->no_sdcard = ON_OFF_AUTO_OFF; + mc->auto_create_sdcard = true;
Except in . hw/core/null-machine.c . hw/arm/xilinx_zynq.c . hw/s390x/s390-virtio-ccw.c where the disabled option is manually removed (since default):
- mc->no_sdcard = ON_OFF_AUTO_ON; + mc->auto_create_sdcard = false; - mc->auto_create_sdcard = false;
and in system/vl.c we change the 'default_sdcard' type to boolean.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-4-philmd@linaro.org>
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8a2f1f92 |
| 25-Nov-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/boards: Explicit no_sdcard=false as ON_OFF_AUTO_OFF
Update MachineClass::no_sdcard default implicit AUTO initialization to explicit OFF. This flag is consumed in system/vl.c::qemu_disable_default
hw/boards: Explicit no_sdcard=false as ON_OFF_AUTO_OFF
Update MachineClass::no_sdcard default implicit AUTO initialization to explicit OFF. This flag is consumed in system/vl.c::qemu_disable_default_devices(). Use this place to assert we don't have anymore AUTO state.
In hw/ppc/e500.c we add the ppce500_machine_class_init() method to initialize once all the inherited classes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-3-philmd@linaro.org>
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