1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/core/sysbus-fdt.h"
33 #include "target/riscv/pmu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/iommu.h"
36 #include "hw/riscv/riscv-iommu-bits.h"
37 #include "hw/riscv/virt.h"
38 #include "hw/riscv/boot.h"
39 #include "hw/riscv/numa.h"
40 #include "kvm/kvm_riscv.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/intc/riscv_aclint.h"
43 #include "hw/intc/riscv_aplic.h"
44 #include "hw/intc/sifive_plic.h"
45 #include "hw/misc/sifive_test.h"
46 #include "hw/platform-bus.h"
47 #include "chardev/char.h"
48 #include "system/device_tree.h"
49 #include "system/system.h"
50 #include "system/tcg.h"
51 #include "system/kvm.h"
52 #include "system/tpm.h"
53 #include "system/qtest.h"
54 #include "hw/pci/pci.h"
55 #include "hw/pci-host/gpex.h"
56 #include "hw/display/ramfb.h"
57 #include "hw/acpi/aml-build.h"
58 #include "qapi/qapi-visit-common.h"
59 #include "hw/virtio/virtio-iommu.h"
60 #include "hw/uefi/var-service-api.h"
61
62 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)63 static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
64 {
65 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
66
67 return riscv_is_kvm_aia_aplic_imsic(msimode);
68 }
69
virt_use_emulated_aplic(RISCVVirtAIAType aia_type)70 static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type)
71 {
72 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
73
74 return riscv_use_emulated_aplic(msimode);
75 }
76
virt_aclint_allowed(void)77 static bool virt_aclint_allowed(void)
78 {
79 return tcg_enabled() || qtest_enabled();
80 }
81
82 static const MemMapEntry virt_memmap[] = {
83 [VIRT_DEBUG] = { 0x0, 0x100 },
84 [VIRT_MROM] = { 0x1000, 0xf000 },
85 [VIRT_TEST] = { 0x100000, 0x1000 },
86 [VIRT_RTC] = { 0x101000, 0x1000 },
87 [VIRT_CLINT] = { 0x2000000, 0x10000 },
88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 },
91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
93 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
94 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
95 [VIRT_UART0] = { 0x10000000, 0x100 },
96 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
97 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
98 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
99 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
100 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
101 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
102 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
103 [VIRT_DRAM] = { 0x80000000, 0x0 },
104 };
105
106 /* PCIe high mmio is fixed for RV32 */
107 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
108 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
109
110 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
111 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
112
113 static MemMapEntry virt_high_pcie_memmap;
114
115 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
116
virt_flash_create1(RISCVVirtState * s,const char * name,const char * alias_prop_name)117 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
118 const char *name,
119 const char *alias_prop_name)
120 {
121 /*
122 * Create a single flash device. We use the same parameters as
123 * the flash devices on the ARM virt board.
124 */
125 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
126
127 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
128 qdev_prop_set_uint8(dev, "width", 4);
129 qdev_prop_set_uint8(dev, "device-width", 2);
130 qdev_prop_set_bit(dev, "big-endian", false);
131 qdev_prop_set_uint16(dev, "id0", 0x89);
132 qdev_prop_set_uint16(dev, "id1", 0x18);
133 qdev_prop_set_uint16(dev, "id2", 0x00);
134 qdev_prop_set_uint16(dev, "id3", 0x00);
135 qdev_prop_set_string(dev, "name", name);
136
137 object_property_add_child(OBJECT(s), name, OBJECT(dev));
138 object_property_add_alias(OBJECT(s), alias_prop_name,
139 OBJECT(dev), "drive");
140
141 return PFLASH_CFI01(dev);
142 }
143
virt_flash_create(RISCVVirtState * s)144 static void virt_flash_create(RISCVVirtState *s)
145 {
146 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
147 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
148 }
149
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)150 static void virt_flash_map1(PFlashCFI01 *flash,
151 hwaddr base, hwaddr size,
152 MemoryRegion *sysmem)
153 {
154 DeviceState *dev = DEVICE(flash);
155
156 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
157 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
158 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
159 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
160
161 memory_region_add_subregion(sysmem, base,
162 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
163 0));
164 }
165
virt_flash_map(RISCVVirtState * s,MemoryRegion * sysmem)166 static void virt_flash_map(RISCVVirtState *s,
167 MemoryRegion *sysmem)
168 {
169 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2;
170 hwaddr flashbase = s->memmap[VIRT_FLASH].base;
171
172 virt_flash_map1(s->flash[0], flashbase, flashsize,
173 sysmem);
174 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
175 sysmem);
176 }
177
create_pcie_irq_map(RISCVVirtState * s,void * fdt,char * nodename,uint32_t irqchip_phandle)178 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
179 uint32_t irqchip_phandle)
180 {
181 int pin, dev;
182 uint32_t irq_map_stride = 0;
183 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS *
184 FDT_MAX_INT_MAP_WIDTH] = {};
185 uint32_t *irq_map = full_irq_map;
186
187 /* This code creates a standard swizzle of interrupts such that
188 * each device's first interrupt is based on it's PCI_SLOT number.
189 * (See pci_swizzle_map_irq_fn())
190 *
191 * We only need one entry per interrupt in the table (not one per
192 * possible slot) seeing the interrupt-map-mask will allow the table
193 * to wrap to any number of devices.
194 */
195 for (dev = 0; dev < PCI_NUM_PINS; dev++) {
196 int devfn = dev * 0x8;
197
198 for (pin = 0; pin < PCI_NUM_PINS; pin++) {
199 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
200 int i = 0;
201
202 /* Fill PCI address cells */
203 irq_map[i] = cpu_to_be32(devfn << 8);
204 i += FDT_PCI_ADDR_CELLS;
205
206 /* Fill PCI Interrupt cells */
207 irq_map[i] = cpu_to_be32(pin + 1);
208 i += FDT_PCI_INT_CELLS;
209
210 /* Fill interrupt controller phandle and cells */
211 irq_map[i++] = cpu_to_be32(irqchip_phandle);
212 irq_map[i++] = cpu_to_be32(irq_nr);
213 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
214 irq_map[i++] = cpu_to_be32(0x4);
215 }
216
217 if (!irq_map_stride) {
218 irq_map_stride = i;
219 }
220 irq_map += irq_map_stride;
221 }
222 }
223
224 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
225 PCI_NUM_PINS * PCI_NUM_PINS *
226 irq_map_stride * sizeof(uint32_t));
227
228 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
229 0x1800, 0, 0, 0x7);
230 }
231
create_fdt_socket_cpus(RISCVVirtState * s,int socket,char * clust_name,uint32_t * phandle,uint32_t * intc_phandles)232 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
233 char *clust_name, uint32_t *phandle,
234 uint32_t *intc_phandles)
235 {
236 int cpu;
237 uint32_t cpu_phandle;
238 MachineState *ms = MACHINE(s);
239 bool is_32_bit = riscv_is_32bit(&s->soc[0]);
240
241 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
242 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
243 int8_t satp_mode_max = cpu_ptr->cfg.max_satp_mode;
244 g_autofree char *cpu_name = NULL;
245 g_autofree char *core_name = NULL;
246 g_autofree char *intc_name = NULL;
247 g_autofree char *sv_name = NULL;
248
249 cpu_phandle = (*phandle)++;
250
251 cpu_name = g_strdup_printf("/cpus/cpu@%d",
252 s->soc[socket].hartid_base + cpu);
253 qemu_fdt_add_subnode(ms->fdt, cpu_name);
254
255 if (satp_mode_max != -1) {
256 sv_name = g_strdup_printf("riscv,%s",
257 satp_mode_str(satp_mode_max, is_32_bit));
258 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
259 }
260
261 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name);
262
263 if (cpu_ptr->cfg.ext_zicbom) {
264 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
265 cpu_ptr->cfg.cbom_blocksize);
266 }
267
268 if (cpu_ptr->cfg.ext_zicboz) {
269 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
270 cpu_ptr->cfg.cboz_blocksize);
271 }
272
273 if (cpu_ptr->cfg.ext_zicbop) {
274 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size",
275 cpu_ptr->cfg.cbop_blocksize);
276 }
277
278 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
279 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
280 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
281 s->soc[socket].hartid_base + cpu);
282 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
283 riscv_socket_fdt_write_id(ms, cpu_name, socket);
284 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
285
286 intc_phandles[cpu] = (*phandle)++;
287
288 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
289 qemu_fdt_add_subnode(ms->fdt, intc_name);
290 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
291 intc_phandles[cpu]);
292 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
293 "riscv,cpu-intc");
294 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
295 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
296
297 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
298 qemu_fdt_add_subnode(ms->fdt, core_name);
299 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
300 }
301 }
302
create_fdt_socket_memory(RISCVVirtState * s,int socket)303 static void create_fdt_socket_memory(RISCVVirtState *s, int socket)
304 {
305 g_autofree char *mem_name = NULL;
306 hwaddr addr;
307 uint64_t size;
308 MachineState *ms = MACHINE(s);
309
310 addr = s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
311 size = riscv_socket_mem_size(ms, socket);
312 mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr);
313 qemu_fdt_add_subnode(ms->fdt, mem_name);
314 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
315 addr >> 32, addr, size >> 32, size);
316 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
317 riscv_socket_fdt_write_id(ms, mem_name, socket);
318 }
319
create_fdt_socket_clint(RISCVVirtState * s,int socket,uint32_t * intc_phandles)320 static void create_fdt_socket_clint(RISCVVirtState *s,
321 int socket,
322 uint32_t *intc_phandles)
323 {
324 int cpu;
325 g_autofree char *clint_name = NULL;
326 g_autofree uint32_t *clint_cells = NULL;
327 unsigned long clint_addr;
328 MachineState *ms = MACHINE(s);
329 static const char * const clint_compat[2] = {
330 "sifive,clint0", "riscv,clint0"
331 };
332
333 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
334
335 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
336 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
337 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
338 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
339 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
340 }
341
342 clint_addr = s->memmap[VIRT_CLINT].base +
343 (s->memmap[VIRT_CLINT].size * socket);
344 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
345 qemu_fdt_add_subnode(ms->fdt, clint_name);
346 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
347 (char **)&clint_compat,
348 ARRAY_SIZE(clint_compat));
349 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
350 0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size);
351 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
352 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
353 riscv_socket_fdt_write_id(ms, clint_name, socket);
354 }
355
create_fdt_socket_aclint(RISCVVirtState * s,int socket,uint32_t * intc_phandles)356 static void create_fdt_socket_aclint(RISCVVirtState *s,
357 int socket,
358 uint32_t *intc_phandles)
359 {
360 int cpu;
361 char *name;
362 unsigned long addr, size;
363 uint32_t aclint_cells_size;
364 g_autofree uint32_t *aclint_mswi_cells = NULL;
365 g_autofree uint32_t *aclint_sswi_cells = NULL;
366 g_autofree uint32_t *aclint_mtimer_cells = NULL;
367 MachineState *ms = MACHINE(s);
368
369 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
370 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
371 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
372
373 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
374 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
375 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
376 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
377 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
378 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
379 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
380 }
381 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
382
383 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
384 addr = s->memmap[VIRT_CLINT].base +
385 (s->memmap[VIRT_CLINT].size * socket);
386 name = g_strdup_printf("/soc/mswi@%lx", addr);
387
388 qemu_fdt_add_subnode(ms->fdt, name);
389 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
390 "riscv,aclint-mswi");
391 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
392 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
393 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
394 aclint_mswi_cells, aclint_cells_size);
395 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
396 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
397 riscv_socket_fdt_write_id(ms, name, socket);
398 g_free(name);
399 }
400
401 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
402 addr = s->memmap[VIRT_CLINT].base +
403 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
404 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
405 } else {
406 addr = s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
407 (s->memmap[VIRT_CLINT].size * socket);
408 size = s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
409 }
410 name = g_strdup_printf("/soc/mtimer@%lx", addr);
411 qemu_fdt_add_subnode(ms->fdt, name);
412 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
413 "riscv,aclint-mtimer");
414 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
415 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
416 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
417 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
418 0x0, RISCV_ACLINT_DEFAULT_MTIME);
419 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
420 aclint_mtimer_cells, aclint_cells_size);
421 riscv_socket_fdt_write_id(ms, name, socket);
422 g_free(name);
423
424 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
425 addr = s->memmap[VIRT_ACLINT_SSWI].base +
426 (s->memmap[VIRT_ACLINT_SSWI].size * socket);
427
428 name = g_strdup_printf("/soc/sswi@%lx", addr);
429 qemu_fdt_add_subnode(ms->fdt, name);
430 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
431 "riscv,aclint-sswi");
432 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
433 0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size);
434 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
435 aclint_sswi_cells, aclint_cells_size);
436 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
437 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
438 riscv_socket_fdt_write_id(ms, name, socket);
439 g_free(name);
440 }
441 }
442
create_fdt_socket_plic(RISCVVirtState * s,int socket,uint32_t * phandle,uint32_t * intc_phandles,uint32_t * plic_phandles)443 static void create_fdt_socket_plic(RISCVVirtState *s,
444 int socket,
445 uint32_t *phandle, uint32_t *intc_phandles,
446 uint32_t *plic_phandles)
447 {
448 int cpu;
449 g_autofree char *plic_name = NULL;
450 g_autofree uint32_t *plic_cells;
451 unsigned long plic_addr;
452 MachineState *ms = MACHINE(s);
453 static const char * const plic_compat[2] = {
454 "sifive,plic-1.0.0", "riscv,plic0"
455 };
456
457 plic_phandles[socket] = (*phandle)++;
458 plic_addr = s->memmap[VIRT_PLIC].base +
459 (s->memmap[VIRT_PLIC].size * socket);
460 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
461 qemu_fdt_add_subnode(ms->fdt, plic_name);
462 qemu_fdt_setprop_cell(ms->fdt, plic_name,
463 "#interrupt-cells", FDT_PLIC_INT_CELLS);
464 qemu_fdt_setprop_cell(ms->fdt, plic_name,
465 "#address-cells", FDT_PLIC_ADDR_CELLS);
466 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
467 (char **)&plic_compat,
468 ARRAY_SIZE(plic_compat));
469 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
470
471 if (kvm_enabled()) {
472 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
473
474 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
475 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
476 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
477 }
478
479 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
480 plic_cells,
481 s->soc[socket].num_harts * sizeof(uint32_t) * 2);
482 } else {
483 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
484
485 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
486 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
487 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
488 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
489 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
490 }
491
492 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
493 plic_cells,
494 s->soc[socket].num_harts * sizeof(uint32_t) * 4);
495 }
496
497 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
498 0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size);
499 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
500 VIRT_IRQCHIP_NUM_SOURCES - 1);
501 riscv_socket_fdt_write_id(ms, plic_name, socket);
502 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
503 plic_phandles[socket]);
504
505 if (!socket) {
506 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
507 s->memmap[VIRT_PLATFORM_BUS].base,
508 s->memmap[VIRT_PLATFORM_BUS].size,
509 VIRT_PLATFORM_BUS_IRQ);
510 }
511 }
512
imsic_num_bits(uint32_t count)513 uint32_t imsic_num_bits(uint32_t count)
514 {
515 uint32_t ret = 0;
516
517 while (BIT(ret) < count) {
518 ret++;
519 }
520
521 return ret;
522 }
523
create_fdt_one_imsic(RISCVVirtState * s,hwaddr base_addr,uint32_t * intc_phandles,uint32_t msi_phandle,bool m_mode,uint32_t imsic_guest_bits)524 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
525 uint32_t *intc_phandles, uint32_t msi_phandle,
526 bool m_mode, uint32_t imsic_guest_bits)
527 {
528 int cpu, socket;
529 g_autofree char *imsic_name = NULL;
530 MachineState *ms = MACHINE(s);
531 int socket_count = riscv_socket_count(ms);
532 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size;
533 g_autofree uint32_t *imsic_cells = NULL;
534 g_autofree uint32_t *imsic_regs = NULL;
535 static const char * const imsic_compat[2] = {
536 "qemu,imsics", "riscv,imsics"
537 };
538
539 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
540 imsic_regs = g_new0(uint32_t, socket_count * 4);
541
542 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
543 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
544 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
545 }
546
547 imsic_max_hart_per_socket = 0;
548 for (socket = 0; socket < socket_count; socket++) {
549 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
550 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
551 s->soc[socket].num_harts;
552 imsic_regs[socket * 4 + 0] = 0;
553 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
554 imsic_regs[socket * 4 + 2] = 0;
555 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
556 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
557 imsic_max_hart_per_socket = s->soc[socket].num_harts;
558 }
559 }
560
561 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx",
562 (unsigned long)base_addr);
563 qemu_fdt_add_subnode(ms->fdt, imsic_name);
564 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible",
565 (char **)&imsic_compat,
566 ARRAY_SIZE(imsic_compat));
567
568 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
569 FDT_IMSIC_INT_CELLS);
570 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
571 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
572 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
573 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
574 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
575 socket_count * sizeof(uint32_t) * 4);
576 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
577 VIRT_IRQCHIP_NUM_MSIS);
578
579 if (imsic_guest_bits) {
580 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
581 imsic_guest_bits);
582 }
583
584 if (socket_count > 1) {
585 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
586 imsic_num_bits(imsic_max_hart_per_socket));
587 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
588 imsic_num_bits(socket_count));
589 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
590 IMSIC_MMIO_GROUP_MIN_SHIFT);
591 }
592 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle);
593 }
594
create_fdt_imsic(RISCVVirtState * s,uint32_t * phandle,uint32_t * intc_phandles,uint32_t * msi_m_phandle,uint32_t * msi_s_phandle)595 static void create_fdt_imsic(RISCVVirtState *s,
596 uint32_t *phandle, uint32_t *intc_phandles,
597 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
598 {
599 *msi_m_phandle = (*phandle)++;
600 *msi_s_phandle = (*phandle)++;
601
602 if (!kvm_enabled()) {
603 /* M-level IMSIC node */
604 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandles,
605 *msi_m_phandle, true, 0);
606 }
607
608 /* S-level IMSIC node */
609 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles,
610 *msi_s_phandle, false,
611 imsic_num_bits(s->aia_guests + 1));
612
613 }
614
615 /* Caller must free string after use */
fdt_get_aplic_nodename(unsigned long aplic_addr)616 static char *fdt_get_aplic_nodename(unsigned long aplic_addr)
617 {
618 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr);
619 }
620
create_fdt_one_aplic(RISCVVirtState * s,int socket,unsigned long aplic_addr,uint32_t aplic_size,uint32_t msi_phandle,uint32_t * intc_phandles,uint32_t aplic_phandle,uint32_t aplic_child_phandle,bool m_mode,int num_harts)621 static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
622 unsigned long aplic_addr, uint32_t aplic_size,
623 uint32_t msi_phandle,
624 uint32_t *intc_phandles,
625 uint32_t aplic_phandle,
626 uint32_t aplic_child_phandle,
627 bool m_mode, int num_harts)
628 {
629 int cpu;
630 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr);
631 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2);
632 MachineState *ms = MACHINE(s);
633 static const char * const aplic_compat[2] = {
634 "qemu,aplic", "riscv,aplic"
635 };
636
637 for (cpu = 0; cpu < num_harts; cpu++) {
638 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
639 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT);
640 }
641
642 qemu_fdt_add_subnode(ms->fdt, aplic_name);
643 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible",
644 (char **)&aplic_compat,
645 ARRAY_SIZE(aplic_compat));
646 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells",
647 FDT_APLIC_ADDR_CELLS);
648 qemu_fdt_setprop_cell(ms->fdt, aplic_name,
649 "#interrupt-cells", FDT_APLIC_INT_CELLS);
650 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
651
652 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
653 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
654 aplic_cells, num_harts * sizeof(uint32_t) * 2);
655 } else {
656 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
657 }
658
659 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
660 0x0, aplic_addr, 0x0, aplic_size);
661 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
662 VIRT_IRQCHIP_NUM_SOURCES);
663
664 if (aplic_child_phandle) {
665 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
666 aplic_child_phandle);
667 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation",
668 aplic_child_phandle, 0x1,
669 VIRT_IRQCHIP_NUM_SOURCES);
670 /*
671 * DEPRECATED_9.1: Compat property kept temporarily
672 * to allow old firmwares to work with AIA. Do *not*
673 * use 'riscv,delegate' in new code: use
674 * 'riscv,delegation' instead.
675 */
676 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
677 aplic_child_phandle, 0x1,
678 VIRT_IRQCHIP_NUM_SOURCES);
679 }
680
681 riscv_socket_fdt_write_id(ms, aplic_name, socket);
682 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle);
683 }
684
create_fdt_socket_aplic(RISCVVirtState * s,int socket,uint32_t msi_m_phandle,uint32_t msi_s_phandle,uint32_t * phandle,uint32_t * intc_phandles,uint32_t * aplic_phandles,int num_harts)685 static void create_fdt_socket_aplic(RISCVVirtState *s,
686 int socket,
687 uint32_t msi_m_phandle,
688 uint32_t msi_s_phandle,
689 uint32_t *phandle,
690 uint32_t *intc_phandles,
691 uint32_t *aplic_phandles,
692 int num_harts)
693 {
694 unsigned long aplic_addr;
695 MachineState *ms = MACHINE(s);
696 uint32_t aplic_m_phandle, aplic_s_phandle;
697
698 aplic_m_phandle = (*phandle)++;
699 aplic_s_phandle = (*phandle)++;
700
701 if (!kvm_enabled()) {
702 /* M-level APLIC node */
703 aplic_addr = s->memmap[VIRT_APLIC_M].base +
704 (s->memmap[VIRT_APLIC_M].size * socket);
705 create_fdt_one_aplic(s, socket, aplic_addr,
706 s->memmap[VIRT_APLIC_M].size,
707 msi_m_phandle, intc_phandles,
708 aplic_m_phandle, aplic_s_phandle,
709 true, num_harts);
710 }
711
712 /* S-level APLIC node */
713 aplic_addr = s->memmap[VIRT_APLIC_S].base +
714 (s->memmap[VIRT_APLIC_S].size * socket);
715 create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].size,
716 msi_s_phandle, intc_phandles,
717 aplic_s_phandle, 0,
718 false, num_harts);
719
720 if (!socket) {
721 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr);
722 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
723 s->memmap[VIRT_PLATFORM_BUS].base,
724 s->memmap[VIRT_PLATFORM_BUS].size,
725 VIRT_PLATFORM_BUS_IRQ);
726 }
727
728 aplic_phandles[socket] = aplic_s_phandle;
729 }
730
create_fdt_pmu(RISCVVirtState * s)731 static void create_fdt_pmu(RISCVVirtState *s)
732 {
733 g_autofree char *pmu_name = g_strdup_printf("/pmu");
734 MachineState *ms = MACHINE(s);
735 RISCVCPU hart = s->soc[0].harts[0];
736
737 qemu_fdt_add_subnode(ms->fdt, pmu_name);
738 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
739 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);
740 }
741
create_fdt_sockets(RISCVVirtState * s,uint32_t * phandle,uint32_t * irq_mmio_phandle,uint32_t * irq_pcie_phandle,uint32_t * irq_virtio_phandle,uint32_t * msi_pcie_phandle)742 static void create_fdt_sockets(RISCVVirtState *s,
743 uint32_t *phandle,
744 uint32_t *irq_mmio_phandle,
745 uint32_t *irq_pcie_phandle,
746 uint32_t *irq_virtio_phandle,
747 uint32_t *msi_pcie_phandle)
748 {
749 int socket, phandle_pos;
750 MachineState *ms = MACHINE(s);
751 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
752 uint32_t xplic_phandles[MAX_NODES];
753 g_autofree uint32_t *intc_phandles = NULL;
754 int socket_count = riscv_socket_count(ms);
755
756 qemu_fdt_add_subnode(ms->fdt, "/cpus");
757 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
758 kvm_enabled() ?
759 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) :
760 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
761 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
762 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
763 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
764
765 intc_phandles = g_new0(uint32_t, ms->smp.cpus);
766
767 phandle_pos = ms->smp.cpus;
768 for (socket = (socket_count - 1); socket >= 0; socket--) {
769 g_autofree char *clust_name = NULL;
770 phandle_pos -= s->soc[socket].num_harts;
771
772 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
773 qemu_fdt_add_subnode(ms->fdt, clust_name);
774
775 create_fdt_socket_cpus(s, socket, clust_name, phandle,
776 &intc_phandles[phandle_pos]);
777
778 create_fdt_socket_memory(s, socket);
779
780 if (virt_aclint_allowed() && s->have_aclint) {
781 create_fdt_socket_aclint(s, socket,
782 &intc_phandles[phandle_pos]);
783 } else if (tcg_enabled()) {
784 create_fdt_socket_clint(s, socket,
785 &intc_phandles[phandle_pos]);
786 }
787 }
788
789 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
790 create_fdt_imsic(s, phandle, intc_phandles,
791 &msi_m_phandle, &msi_s_phandle);
792 *msi_pcie_phandle = msi_s_phandle;
793 }
794
795 /*
796 * With KVM AIA aplic-imsic, using an irqchip without split
797 * mode, we'll use only one APLIC instance.
798 */
799 if (!virt_use_emulated_aplic(s->aia_type)) {
800 create_fdt_socket_aplic(s, 0,
801 msi_m_phandle, msi_s_phandle, phandle,
802 &intc_phandles[0], xplic_phandles,
803 ms->smp.cpus);
804
805 *irq_mmio_phandle = xplic_phandles[0];
806 *irq_virtio_phandle = xplic_phandles[0];
807 *irq_pcie_phandle = xplic_phandles[0];
808 } else {
809 phandle_pos = ms->smp.cpus;
810 for (socket = (socket_count - 1); socket >= 0; socket--) {
811 phandle_pos -= s->soc[socket].num_harts;
812
813 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
814 create_fdt_socket_plic(s, socket, phandle,
815 &intc_phandles[phandle_pos],
816 xplic_phandles);
817 } else {
818 create_fdt_socket_aplic(s, socket,
819 msi_m_phandle, msi_s_phandle, phandle,
820 &intc_phandles[phandle_pos],
821 xplic_phandles,
822 s->soc[socket].num_harts);
823 }
824 }
825
826 for (socket = 0; socket < socket_count; socket++) {
827 if (socket == 0) {
828 *irq_mmio_phandle = xplic_phandles[socket];
829 *irq_virtio_phandle = xplic_phandles[socket];
830 *irq_pcie_phandle = xplic_phandles[socket];
831 }
832 if (socket == 1) {
833 *irq_virtio_phandle = xplic_phandles[socket];
834 *irq_pcie_phandle = xplic_phandles[socket];
835 }
836 if (socket == 2) {
837 *irq_pcie_phandle = xplic_phandles[socket];
838 }
839 }
840 }
841
842 riscv_socket_fdt_write_distance_matrix(ms);
843 }
844
create_fdt_virtio(RISCVVirtState * s,uint32_t irq_virtio_phandle)845 static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle)
846 {
847 int i;
848 MachineState *ms = MACHINE(s);
849 hwaddr virtio_base = s->memmap[VIRT_VIRTIO].base;
850
851 for (i = 0; i < VIRTIO_COUNT; i++) {
852 g_autofree char *name = NULL;
853 uint64_t size = s->memmap[VIRT_VIRTIO].size;
854 hwaddr addr = virtio_base + i * size;
855
856 name = g_strdup_printf("/soc/virtio_mmio@%"HWADDR_PRIx, addr);
857
858 qemu_fdt_add_subnode(ms->fdt, name);
859 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
860 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
861 0x0, addr,
862 0x0, size);
863 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
864 irq_virtio_phandle);
865 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
866 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
867 VIRTIO_IRQ + i);
868 } else {
869 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
870 VIRTIO_IRQ + i, 0x4);
871 }
872 }
873 }
874
create_fdt_pcie(RISCVVirtState * s,uint32_t irq_pcie_phandle,uint32_t msi_pcie_phandle,uint32_t iommu_sys_phandle)875 static void create_fdt_pcie(RISCVVirtState *s,
876 uint32_t irq_pcie_phandle,
877 uint32_t msi_pcie_phandle,
878 uint32_t iommu_sys_phandle)
879 {
880 g_autofree char *name = NULL;
881 MachineState *ms = MACHINE(s);
882
883 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
884 s->memmap[VIRT_PCIE_ECAM].base);
885 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
886 FDT_PCI_ADDR_CELLS);
887 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
888 FDT_PCI_INT_CELLS);
889 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
890 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
891 "pci-host-ecam-generic");
892 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
893 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
894 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
895 s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
896 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
897 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
898 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
899 }
900 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
901 s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size);
902 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
903 1, FDT_PCI_RANGE_IOPORT, 2, 0,
904 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,
905 1, FDT_PCI_RANGE_MMIO,
906 2, s->memmap[VIRT_PCIE_MMIO].base,
907 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].size,
908 1, FDT_PCI_RANGE_MMIO_64BIT,
909 2, virt_high_pcie_memmap.base,
910 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
911
912 if (virt_is_iommu_sys_enabled(s)) {
913 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map",
914 0, iommu_sys_phandle, 0, 0, 0,
915 iommu_sys_phandle, 0, 0xffff);
916 }
917
918 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
919 }
920
create_fdt_reset(RISCVVirtState * s,uint32_t * phandle)921 static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle)
922 {
923 char *name;
924 uint32_t test_phandle;
925 MachineState *ms = MACHINE(s);
926
927 test_phandle = (*phandle)++;
928 name = g_strdup_printf("/soc/test@%"HWADDR_PRIx,
929 s->memmap[VIRT_TEST].base);
930 qemu_fdt_add_subnode(ms->fdt, name);
931 {
932 static const char * const compat[3] = {
933 "sifive,test1", "sifive,test0", "syscon"
934 };
935 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
936 (char **)&compat, ARRAY_SIZE(compat));
937 }
938 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
939 0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size);
940 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
941 test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
942 g_free(name);
943
944 name = g_strdup_printf("/reboot");
945 qemu_fdt_add_subnode(ms->fdt, name);
946 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
947 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
948 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
949 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
950 g_free(name);
951
952 name = g_strdup_printf("/poweroff");
953 qemu_fdt_add_subnode(ms->fdt, name);
954 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
955 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
956 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
957 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
958 g_free(name);
959 }
960
create_fdt_uart(RISCVVirtState * s,uint32_t irq_mmio_phandle)961 static void create_fdt_uart(RISCVVirtState *s,
962 uint32_t irq_mmio_phandle)
963 {
964 g_autofree char *name = NULL;
965 MachineState *ms = MACHINE(s);
966
967 name = g_strdup_printf("/soc/serial@%"HWADDR_PRIx,
968 s->memmap[VIRT_UART0].base);
969 qemu_fdt_add_subnode(ms->fdt, name);
970 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
971 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
972 0x0, s->memmap[VIRT_UART0].base,
973 0x0, s->memmap[VIRT_UART0].size);
974 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
975 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
976 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
977 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
978 } else {
979 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
980 }
981
982 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
983 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name);
984 }
985
create_fdt_rtc(RISCVVirtState * s,uint32_t irq_mmio_phandle)986 static void create_fdt_rtc(RISCVVirtState *s,
987 uint32_t irq_mmio_phandle)
988 {
989 g_autofree char *name = NULL;
990 MachineState *ms = MACHINE(s);
991
992 name = g_strdup_printf("/soc/rtc@%"HWADDR_PRIx,
993 s->memmap[VIRT_RTC].base);
994 qemu_fdt_add_subnode(ms->fdt, name);
995 qemu_fdt_setprop_string(ms->fdt, name, "compatible",
996 "google,goldfish-rtc");
997 qemu_fdt_setprop_cells(ms->fdt, name, "reg",
998 0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size);
999 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
1000 irq_mmio_phandle);
1001 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1002 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
1003 } else {
1004 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
1005 }
1006 }
1007
create_fdt_flash(RISCVVirtState * s)1008 static void create_fdt_flash(RISCVVirtState *s)
1009 {
1010 MachineState *ms = MACHINE(s);
1011 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2;
1012 hwaddr flashbase = s->memmap[VIRT_FLASH].base;
1013 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase);
1014
1015 qemu_fdt_add_subnode(ms->fdt, name);
1016 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
1017 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
1018 2, flashbase, 2, flashsize,
1019 2, flashbase + flashsize, 2, flashsize);
1020 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
1021 }
1022
create_fdt_fw_cfg(RISCVVirtState * s)1023 static void create_fdt_fw_cfg(RISCVVirtState *s)
1024 {
1025 MachineState *ms = MACHINE(s);
1026 hwaddr base = s->memmap[VIRT_FW_CFG].base;
1027 hwaddr size = s->memmap[VIRT_FW_CFG].size;
1028 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1029
1030 qemu_fdt_add_subnode(ms->fdt, nodename);
1031 qemu_fdt_setprop_string(ms->fdt, nodename,
1032 "compatible", "qemu,fw-cfg-mmio");
1033 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1034 2, base, 2, size);
1035 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1036 }
1037
create_fdt_virtio_iommu(RISCVVirtState * s,uint16_t bdf)1038 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
1039 {
1040 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1041 void *fdt = MACHINE(s)->fdt;
1042 uint32_t iommu_phandle;
1043 g_autofree char *iommu_node = NULL;
1044 g_autofree char *pci_node = NULL;
1045
1046 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
1047 s->memmap[VIRT_PCIE_ECAM].base);
1048 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node,
1049 PCI_SLOT(bdf), PCI_FUNC(bdf));
1050 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
1051
1052 qemu_fdt_add_subnode(fdt, iommu_node);
1053
1054 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat));
1055 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg",
1056 1, bdf << 8, 1, 0, 1, 0,
1057 1, 0, 1, 0);
1058 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1059 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1060
1061 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
1062 0, iommu_phandle, 0, bdf,
1063 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
1064 }
1065
create_fdt_iommu_sys(RISCVVirtState * s,uint32_t irq_chip,uint32_t msi_phandle,uint32_t * iommu_sys_phandle)1066 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
1067 uint32_t msi_phandle,
1068 uint32_t *iommu_sys_phandle)
1069 {
1070 const char comp[] = "riscv,iommu";
1071 void *fdt = MACHINE(s)->fdt;
1072 uint32_t iommu_phandle;
1073 g_autofree char *iommu_node = NULL;
1074 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base;
1075 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size;
1076 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = {
1077 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,
1078 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,
1079 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,
1080 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,
1081 };
1082
1083 iommu_node = g_strdup_printf("/soc/iommu@%x",
1084 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base);
1085 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
1086 qemu_fdt_add_subnode(fdt, iommu_node);
1087
1088 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
1089 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1090 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1091
1092 qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
1093 addr >> 32, addr, size >> 32, size);
1094 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
1095
1096 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
1097 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,
1098 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,
1099 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
1100 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
1101
1102 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
1103
1104 *iommu_sys_phandle = iommu_phandle;
1105 }
1106
create_fdt_iommu(RISCVVirtState * s,uint16_t bdf)1107 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
1108 {
1109 const char comp[] = "riscv,pci-iommu";
1110 void *fdt = MACHINE(s)->fdt;
1111 uint32_t iommu_phandle;
1112 g_autofree char *iommu_node = NULL;
1113 g_autofree char *pci_node = NULL;
1114
1115 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
1116 s->memmap[VIRT_PCIE_ECAM].base);
1117 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf);
1118 iommu_phandle = qemu_fdt_alloc_phandle(fdt);
1119 qemu_fdt_add_subnode(fdt, iommu_node);
1120
1121 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
1122 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
1123 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
1124 qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
1125 bdf << 8, 0, 0, 0, 0);
1126 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
1127 0, iommu_phandle, 0, bdf,
1128 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
1129 s->pci_iommu_bdf = bdf;
1130 }
1131
finalize_fdt(RISCVVirtState * s)1132 static void finalize_fdt(RISCVVirtState *s)
1133 {
1134 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
1135 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
1136 uint32_t iommu_sys_phandle = 1;
1137
1138 create_fdt_sockets(s, &phandle, &irq_mmio_phandle,
1139 &irq_pcie_phandle, &irq_virtio_phandle,
1140 &msi_pcie_phandle);
1141
1142 create_fdt_virtio(s, irq_virtio_phandle);
1143
1144 if (virt_is_iommu_sys_enabled(s)) {
1145 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,
1146 &iommu_sys_phandle);
1147 }
1148 create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle,
1149 iommu_sys_phandle);
1150
1151 create_fdt_reset(s, &phandle);
1152
1153 create_fdt_uart(s, irq_mmio_phandle);
1154
1155 create_fdt_rtc(s, irq_mmio_phandle);
1156 }
1157
create_fdt(RISCVVirtState * s)1158 static void create_fdt(RISCVVirtState *s)
1159 {
1160 MachineState *ms = MACHINE(s);
1161 uint8_t rng_seed[32];
1162 g_autofree char *name = NULL;
1163
1164 ms->fdt = create_device_tree(&s->fdt_size);
1165 if (!ms->fdt) {
1166 error_report("create_device_tree() failed");
1167 exit(1);
1168 }
1169
1170 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
1171 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
1172 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
1173 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
1174
1175 qemu_fdt_add_subnode(ms->fdt, "/soc");
1176 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
1177 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
1178 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
1179 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
1180
1181 /*
1182 * The "/soc/pci@..." node is needed for PCIE hotplugs
1183 * that might happen before finalize_fdt().
1184 */
1185 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx,
1186 s->memmap[VIRT_PCIE_ECAM].base);
1187 qemu_fdt_add_subnode(ms->fdt, name);
1188
1189 qemu_fdt_add_subnode(ms->fdt, "/chosen");
1190
1191 /* Pass seed to RNG */
1192 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
1193 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
1194 rng_seed, sizeof(rng_seed));
1195
1196 qemu_fdt_add_subnode(ms->fdt, "/aliases");
1197
1198 create_fdt_flash(s);
1199 create_fdt_fw_cfg(s);
1200 create_fdt_pmu(s);
1201 }
1202
gpex_pcie_init(MemoryRegion * sys_mem,DeviceState * irqchip,RISCVVirtState * s)1203 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1204 DeviceState *irqchip,
1205 RISCVVirtState *s)
1206 {
1207 DeviceState *dev;
1208 MemoryRegion *ecam_alias, *ecam_reg;
1209 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1210 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
1211 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
1212 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
1213 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
1214 hwaddr high_mmio_base = virt_high_pcie_memmap.base;
1215 hwaddr high_mmio_size = virt_high_pcie_memmap.size;
1216 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
1217 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
1218 qemu_irq irq;
1219 int i;
1220
1221 dev = qdev_new(TYPE_GPEX_HOST);
1222
1223 /* Set GPEX object properties for the virt machine */
1224 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE,
1225 ecam_base, NULL);
1226 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE,
1227 ecam_size, NULL);
1228 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE,
1229 mmio_base, NULL);
1230 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE,
1231 mmio_size, NULL);
1232 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE,
1233 high_mmio_base, NULL);
1234 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE,
1235 high_mmio_size, NULL);
1236 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE,
1237 pio_base, NULL);
1238 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE,
1239 pio_size, NULL);
1240
1241 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1242
1243 ecam_alias = g_new0(MemoryRegion, 1);
1244 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1245 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1246 ecam_reg, 0, ecam_size);
1247 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1248
1249 mmio_alias = g_new0(MemoryRegion, 1);
1250 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1251 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1252 mmio_reg, mmio_base, mmio_size);
1253 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1254
1255 /* Map high MMIO space */
1256 high_mmio_alias = g_new0(MemoryRegion, 1);
1257 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1258 mmio_reg, high_mmio_base, high_mmio_size);
1259 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1260 high_mmio_alias);
1261
1262 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1263
1264 for (i = 0; i < PCI_NUM_PINS; i++) {
1265 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1266
1267 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1268 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1269 }
1270
1271 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus;
1272 return dev;
1273 }
1274
create_fw_cfg(const MachineState * ms,hwaddr base)1275 static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base)
1276 {
1277 FWCfgState *fw_cfg;
1278
1279 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1280 &address_space_memory);
1281 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1282
1283 return fw_cfg;
1284 }
1285
virt_create_plic(const MemMapEntry * memmap,int socket,int base_hartid,int hart_count)1286 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1287 int base_hartid, int hart_count)
1288 {
1289 g_autofree char *plic_hart_config = NULL;
1290
1291 /* Per-socket PLIC hart topology configuration string */
1292 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1293
1294 /* Per-socket PLIC */
1295 return sifive_plic_create(
1296 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1297 plic_hart_config, hart_count, base_hartid,
1298 VIRT_IRQCHIP_NUM_SOURCES,
1299 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1300 VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE,
1301 VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE,
1302 VIRT_PLIC_CONTEXT_BASE,
1303 VIRT_PLIC_CONTEXT_STRIDE,
1304 memmap[VIRT_PLIC].size);
1305 }
1306
virt_create_aia(RISCVVirtAIAType aia_type,int aia_guests,const MemMapEntry * memmap,int socket,int base_hartid,int hart_count)1307 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1308 const MemMapEntry *memmap, int socket,
1309 int base_hartid, int hart_count)
1310 {
1311 int i;
1312 hwaddr addr = 0;
1313 uint32_t guest_bits;
1314 DeviceState *aplic_s = NULL;
1315 DeviceState *aplic_m = NULL;
1316 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
1317
1318 if (msimode) {
1319 if (!kvm_enabled()) {
1320 /* Per-socket M-level IMSICs */
1321 addr = memmap[VIRT_IMSIC_M].base +
1322 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1323 for (i = 0; i < hart_count; i++) {
1324 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1325 base_hartid + i, true, 1,
1326 VIRT_IRQCHIP_NUM_MSIS);
1327 }
1328 }
1329
1330 /* Per-socket S-level IMSICs */
1331 guest_bits = imsic_num_bits(aia_guests + 1);
1332 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1333 for (i = 0; i < hart_count; i++) {
1334 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1335 base_hartid + i, false, 1 + aia_guests,
1336 VIRT_IRQCHIP_NUM_MSIS);
1337 }
1338 }
1339
1340 if (!kvm_enabled()) {
1341 /* Per-socket M-level APLIC */
1342 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
1343 socket * memmap[VIRT_APLIC_M].size,
1344 memmap[VIRT_APLIC_M].size,
1345 (msimode) ? 0 : base_hartid,
1346 (msimode) ? 0 : hart_count,
1347 VIRT_IRQCHIP_NUM_SOURCES,
1348 VIRT_IRQCHIP_NUM_PRIO_BITS,
1349 msimode, true, NULL);
1350 }
1351
1352 /* Per-socket S-level APLIC */
1353 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
1354 socket * memmap[VIRT_APLIC_S].size,
1355 memmap[VIRT_APLIC_S].size,
1356 (msimode) ? 0 : base_hartid,
1357 (msimode) ? 0 : hart_count,
1358 VIRT_IRQCHIP_NUM_SOURCES,
1359 VIRT_IRQCHIP_NUM_PRIO_BITS,
1360 msimode, false, aplic_m);
1361
1362 if (kvm_enabled() && msimode) {
1363 riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);
1364 }
1365
1366 return kvm_enabled() ? aplic_s : aplic_m;
1367 }
1368
create_platform_bus(RISCVVirtState * s,DeviceState * irqchip)1369 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
1370 {
1371 DeviceState *dev;
1372 SysBusDevice *sysbus;
1373 int i;
1374 MemoryRegion *sysmem = get_system_memory();
1375
1376 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1377 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1378 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
1379 qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size);
1380 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1381 s->platform_bus_dev = dev;
1382
1383 sysbus = SYS_BUS_DEVICE(dev);
1384 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
1385 int irq = VIRT_PLATFORM_BUS_IRQ + i;
1386 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
1387 }
1388
1389 memory_region_add_subregion(sysmem,
1390 s->memmap[VIRT_PLATFORM_BUS].base,
1391 sysbus_mmio_get_region(sysbus, 0));
1392 }
1393
virt_build_smbios(RISCVVirtState * s)1394 static void virt_build_smbios(RISCVVirtState *s)
1395 {
1396 MachineClass *mc = MACHINE_GET_CLASS(s);
1397 MachineState *ms = MACHINE(s);
1398 uint8_t *smbios_tables, *smbios_anchor;
1399 size_t smbios_tables_len, smbios_anchor_len;
1400 struct smbios_phys_mem_area mem_array;
1401 const char *product = "QEMU Virtual Machine";
1402
1403 if (kvm_enabled()) {
1404 product = "KVM Virtual Machine";
1405 }
1406
1407 smbios_set_defaults("QEMU", product, mc->name);
1408
1409 if (riscv_is_32bit(&s->soc[0])) {
1410 smbios_set_default_processor_family(0x200);
1411 } else {
1412 smbios_set_default_processor_family(0x201);
1413 }
1414
1415 /* build the array of physical mem area from base_memmap */
1416 mem_array.address = s->memmap[VIRT_DRAM].base;
1417 mem_array.length = ms->ram_size;
1418
1419 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64,
1420 &mem_array, 1,
1421 &smbios_tables, &smbios_tables_len,
1422 &smbios_anchor, &smbios_anchor_len,
1423 &error_fatal);
1424
1425 if (smbios_anchor) {
1426 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables",
1427 smbios_tables, smbios_tables_len);
1428 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor",
1429 smbios_anchor, smbios_anchor_len);
1430 }
1431 }
1432
virt_machine_done(Notifier * notifier,void * data)1433 static void virt_machine_done(Notifier *notifier, void *data)
1434 {
1435 RISCVVirtState *s = container_of(notifier, RISCVVirtState,
1436 machine_done);
1437 MachineState *machine = MACHINE(s);
1438 hwaddr start_addr = s->memmap[VIRT_DRAM].base;
1439 target_ulong firmware_end_addr, kernel_start_addr;
1440 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
1441 uint64_t fdt_load_addr;
1442 uint64_t kernel_entry = 0;
1443 BlockBackend *pflash_blk0;
1444 RISCVBootInfo boot_info;
1445
1446 /*
1447 * An user provided dtb must include everything, including
1448 * dynamic sysbus devices. Our FDT needs to be finalized.
1449 */
1450 if (machine->dtb == NULL) {
1451 finalize_fdt(s);
1452 }
1453
1454 /*
1455 * Only direct boot kernel is currently supported for KVM VM,
1456 * so the "-bios" parameter is not supported when KVM is enabled.
1457 */
1458 if (kvm_enabled()) {
1459 if (machine->firmware) {
1460 if (strcmp(machine->firmware, "none")) {
1461 error_report("Machine mode firmware is not supported in "
1462 "combination with KVM.");
1463 exit(1);
1464 }
1465 } else {
1466 machine->firmware = g_strdup("none");
1467 }
1468 }
1469
1470 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
1471 &start_addr, NULL);
1472
1473 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);
1474 if (pflash_blk0) {
1475 if (machine->firmware && !strcmp(machine->firmware, "none") &&
1476 !kvm_enabled()) {
1477 /*
1478 * Pflash was supplied but bios is none and not KVM guest,
1479 * let's overwrite the address we jump to after reset to
1480 * the base of the flash.
1481 */
1482 start_addr = s->memmap[VIRT_FLASH].base;
1483 } else {
1484 /*
1485 * Pflash was supplied but either KVM guest or bios is not none.
1486 * In this case, base of the flash would contain S-mode payload.
1487 */
1488 riscv_setup_firmware_boot(machine);
1489 kernel_entry = s->memmap[VIRT_FLASH].base;
1490 }
1491 }
1492
1493 riscv_boot_info_init(&boot_info, &s->soc[0]);
1494
1495 if (machine->kernel_filename && !kernel_entry) {
1496 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
1497 firmware_end_addr);
1498 riscv_load_kernel(machine, &boot_info, kernel_start_addr,
1499 true, NULL);
1500 kernel_entry = boot_info.image_low_addr;
1501 }
1502
1503 fdt_load_addr = riscv_compute_fdt_addr(s->memmap[VIRT_DRAM].base,
1504 s->memmap[VIRT_DRAM].size,
1505 machine, &boot_info);
1506 riscv_load_fdt(fdt_load_addr, machine->fdt);
1507
1508 /* load the reset vector */
1509 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1510 s->memmap[VIRT_MROM].base,
1511 s->memmap[VIRT_MROM].size, kernel_entry,
1512 fdt_load_addr);
1513
1514 /*
1515 * Only direct boot kernel is currently supported for KVM VM,
1516 * So here setup kernel start address and fdt address.
1517 * TODO:Support firmware loading and integrate to TCG start
1518 */
1519 if (kvm_enabled()) {
1520 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1521 }
1522
1523 virt_build_smbios(s);
1524
1525 if (virt_is_acpi_enabled(s)) {
1526 virt_acpi_setup(s);
1527 }
1528 }
1529
virt_machine_init(MachineState * machine)1530 static void virt_machine_init(MachineState *machine)
1531 {
1532 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1533 MemoryRegion *system_memory = get_system_memory();
1534 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1535 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1536 int i, base_hartid, hart_count;
1537 int socket_count = riscv_socket_count(machine);
1538
1539 s->memmap = virt_memmap;
1540
1541 /* Check socket count limit */
1542 if (VIRT_SOCKETS_MAX < socket_count) {
1543 error_report("number of sockets/nodes should be less than %d",
1544 VIRT_SOCKETS_MAX);
1545 exit(1);
1546 }
1547
1548 if (!virt_aclint_allowed() && s->have_aclint) {
1549 error_report("'aclint' is only available with TCG acceleration");
1550 exit(1);
1551 }
1552
1553 /* Initialize sockets */
1554 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1555 for (i = 0; i < socket_count; i++) {
1556 g_autofree char *soc_name = g_strdup_printf("soc%d", i);
1557
1558 if (!riscv_socket_check_hartids(machine, i)) {
1559 error_report("discontinuous hartids in socket%d", i);
1560 exit(1);
1561 }
1562
1563 base_hartid = riscv_socket_first_hartid(machine, i);
1564 if (base_hartid < 0) {
1565 error_report("can't find hartid base for socket%d", i);
1566 exit(1);
1567 }
1568
1569 hart_count = riscv_socket_hart_count(machine, i);
1570 if (hart_count < 0) {
1571 error_report("can't find hart count for socket%d", i);
1572 exit(1);
1573 }
1574
1575 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1576 TYPE_RISCV_HART_ARRAY);
1577 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1578 machine->cpu_type, &error_abort);
1579 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1580 base_hartid, &error_abort);
1581 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1582 hart_count, &error_abort);
1583 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);
1584
1585 if (virt_aclint_allowed() && s->have_aclint) {
1586 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1587 /* Per-socket ACLINT MTIMER */
1588 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
1589 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1590 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1591 base_hartid, hart_count,
1592 RISCV_ACLINT_DEFAULT_MTIMECMP,
1593 RISCV_ACLINT_DEFAULT_MTIME,
1594 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1595 } else {
1596 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1597 riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base +
1598 i * s->memmap[VIRT_CLINT].size,
1599 base_hartid, hart_count, false);
1600 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
1601 i * s->memmap[VIRT_CLINT].size +
1602 RISCV_ACLINT_SWI_SIZE,
1603 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1604 base_hartid, hart_count,
1605 RISCV_ACLINT_DEFAULT_MTIMECMP,
1606 RISCV_ACLINT_DEFAULT_MTIME,
1607 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1608 riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base +
1609 i * s->memmap[VIRT_ACLINT_SSWI].size,
1610 base_hartid, hart_count, true);
1611 }
1612 } else if (tcg_enabled()) {
1613 /* Per-socket SiFive CLINT */
1614 riscv_aclint_swi_create(
1615 s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size,
1616 base_hartid, hart_count, false);
1617 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base +
1618 i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1619 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1620 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1621 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1622 }
1623
1624 /* Per-socket interrupt controller */
1625 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1626 s->irqchip[i] = virt_create_plic(s->memmap, i,
1627 base_hartid, hart_count);
1628 } else {
1629 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1630 s->memmap, i, base_hartid,
1631 hart_count);
1632 }
1633
1634 /* Try to use different IRQCHIP instance based device type */
1635 if (i == 0) {
1636 mmio_irqchip = s->irqchip[i];
1637 virtio_irqchip = s->irqchip[i];
1638 pcie_irqchip = s->irqchip[i];
1639 }
1640 if (i == 1) {
1641 virtio_irqchip = s->irqchip[i];
1642 pcie_irqchip = s->irqchip[i];
1643 }
1644 if (i == 2) {
1645 pcie_irqchip = s->irqchip[i];
1646 }
1647 }
1648
1649 if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
1650 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
1651 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
1652 s->memmap[VIRT_APLIC_S].base,
1653 s->memmap[VIRT_IMSIC_S].base,
1654 s->aia_guests);
1655 }
1656
1657 if (riscv_is_32bit(&s->soc[0])) {
1658 #if HOST_LONG_BITS == 64
1659 /* limit RAM size in a 32-bit system */
1660 if (machine->ram_size > 10 * GiB) {
1661 machine->ram_size = 10 * GiB;
1662 error_report("Limiting RAM size to 10 GiB");
1663 }
1664 #endif
1665 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1666 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1667 } else {
1668 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1669 virt_high_pcie_memmap.base = s->memmap[VIRT_DRAM].base +
1670 machine->ram_size;
1671 virt_high_pcie_memmap.base =
1672 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1673 }
1674
1675 /* register system main memory (actual RAM) */
1676 memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base,
1677 machine->ram);
1678
1679 /* boot rom */
1680 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1681 s->memmap[VIRT_MROM].size, &error_fatal);
1682 memory_region_add_subregion(system_memory, s->memmap[VIRT_MROM].base,
1683 mask_rom);
1684
1685 /*
1686 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
1687 * device tree cannot be altered and we get FDT_ERR_NOSPACE.
1688 */
1689 s->fw_cfg = create_fw_cfg(machine, s->memmap[VIRT_FW_CFG].base);
1690 rom_set_fw(s->fw_cfg);
1691
1692 /* SiFive Test MMIO device */
1693 sifive_test_create(s->memmap[VIRT_TEST].base);
1694
1695 /* VirtIO MMIO devices */
1696 for (i = 0; i < VIRTIO_COUNT; i++) {
1697 sysbus_create_simple("virtio-mmio",
1698 s->memmap[VIRT_VIRTIO].base + i * s->memmap[VIRT_VIRTIO].size,
1699 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
1700 }
1701
1702 gpex_pcie_init(system_memory, pcie_irqchip, s);
1703
1704 create_platform_bus(s, mmio_irqchip);
1705
1706 serial_mm_init(system_memory, s->memmap[VIRT_UART0].base,
1707 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193,
1708 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1709
1710 sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base,
1711 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ));
1712
1713 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1714 /* Map legacy -drive if=pflash to machine properties */
1715 pflash_cfi01_legacy_drive(s->flash[i],
1716 drive_get(IF_PFLASH, 0, i));
1717 }
1718 virt_flash_map(s, system_memory);
1719
1720 /* load/create device tree */
1721 if (machine->dtb) {
1722 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
1723 if (!machine->fdt) {
1724 error_report("load_device_tree() failed");
1725 exit(1);
1726 }
1727 } else {
1728 create_fdt(s);
1729 }
1730
1731 if (virt_is_iommu_sys_enabled(s)) {
1732 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);
1733
1734 object_property_set_uint(OBJECT(iommu_sys), "addr",
1735 s->memmap[VIRT_IOMMU_SYS].base,
1736 &error_fatal);
1737 object_property_set_uint(OBJECT(iommu_sys), "base-irq",
1738 IOMMU_SYS_IRQ,
1739 &error_fatal);
1740 object_property_set_link(OBJECT(iommu_sys), "irqchip",
1741 OBJECT(mmio_irqchip),
1742 &error_fatal);
1743
1744 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
1745 }
1746
1747 s->machine_done.notify = virt_machine_done;
1748 qemu_add_machine_init_done_notifier(&s->machine_done);
1749 }
1750
virt_machine_instance_init(Object * obj)1751 static void virt_machine_instance_init(Object *obj)
1752 {
1753 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1754
1755 virt_flash_create(s);
1756
1757 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
1758 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
1759 s->acpi = ON_OFF_AUTO_AUTO;
1760 s->iommu_sys = ON_OFF_AUTO_AUTO;
1761 }
1762
virt_get_aia_guests(Object * obj,Error ** errp)1763 static char *virt_get_aia_guests(Object *obj, Error **errp)
1764 {
1765 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1766
1767 return g_strdup_printf("%d", s->aia_guests);
1768 }
1769
virt_set_aia_guests(Object * obj,const char * val,Error ** errp)1770 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1771 {
1772 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1773
1774 s->aia_guests = atoi(val);
1775 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1776 error_setg(errp, "Invalid number of AIA IMSIC guests");
1777 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1778 VIRT_IRQCHIP_MAX_GUESTS);
1779 }
1780 }
1781
virt_get_aia(Object * obj,Error ** errp)1782 static char *virt_get_aia(Object *obj, Error **errp)
1783 {
1784 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1785 const char *val;
1786
1787 switch (s->aia_type) {
1788 case VIRT_AIA_TYPE_APLIC:
1789 val = "aplic";
1790 break;
1791 case VIRT_AIA_TYPE_APLIC_IMSIC:
1792 val = "aplic-imsic";
1793 break;
1794 default:
1795 val = "none";
1796 break;
1797 };
1798
1799 return g_strdup(val);
1800 }
1801
virt_set_aia(Object * obj,const char * val,Error ** errp)1802 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1803 {
1804 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1805
1806 if (!strcmp(val, "none")) {
1807 s->aia_type = VIRT_AIA_TYPE_NONE;
1808 } else if (!strcmp(val, "aplic")) {
1809 s->aia_type = VIRT_AIA_TYPE_APLIC;
1810 } else if (!strcmp(val, "aplic-imsic")) {
1811 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1812 } else {
1813 error_setg(errp, "Invalid AIA interrupt controller type");
1814 error_append_hint(errp, "Valid values are none, aplic, and "
1815 "aplic-imsic.\n");
1816 }
1817 }
1818
virt_get_aclint(Object * obj,Error ** errp)1819 static bool virt_get_aclint(Object *obj, Error **errp)
1820 {
1821 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1822
1823 return s->have_aclint;
1824 }
1825
virt_set_aclint(Object * obj,bool value,Error ** errp)1826 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1827 {
1828 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1829
1830 s->have_aclint = value;
1831 }
1832
virt_is_iommu_sys_enabled(RISCVVirtState * s)1833 bool virt_is_iommu_sys_enabled(RISCVVirtState *s)
1834 {
1835 return s->iommu_sys == ON_OFF_AUTO_ON;
1836 }
1837
virt_get_iommu_sys(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1838 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name,
1839 void *opaque, Error **errp)
1840 {
1841 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1842 OnOffAuto iommu_sys = s->iommu_sys;
1843
1844 visit_type_OnOffAuto(v, name, &iommu_sys, errp);
1845 }
1846
virt_set_iommu_sys(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1847 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
1848 void *opaque, Error **errp)
1849 {
1850 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1851
1852 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
1853 }
1854
virt_is_acpi_enabled(RISCVVirtState * s)1855 bool virt_is_acpi_enabled(RISCVVirtState *s)
1856 {
1857 return s->acpi != ON_OFF_AUTO_OFF;
1858 }
1859
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1860 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
1861 void *opaque, Error **errp)
1862 {
1863 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1864 OnOffAuto acpi = s->acpi;
1865
1866 visit_type_OnOffAuto(v, name, &acpi, errp);
1867 }
1868
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)1869 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
1870 void *opaque, Error **errp)
1871 {
1872 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1873
1874 visit_type_OnOffAuto(v, name, &s->acpi, errp);
1875 }
1876
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)1877 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1878 DeviceState *dev)
1879 {
1880 MachineClass *mc = MACHINE_GET_CLASS(machine);
1881 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1882
1883 if (device_is_dynamic_sysbus(mc, dev) ||
1884 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1885 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
1886 s->iommu_sys = ON_OFF_AUTO_OFF;
1887 return HOTPLUG_HANDLER(machine);
1888 }
1889
1890 return NULL;
1891 }
1892
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)1893 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1894 DeviceState *dev, Error **errp)
1895 {
1896 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
1897
1898 if (s->platform_bus_dev) {
1899 MachineClass *mc = MACHINE_GET_CLASS(s);
1900
1901 if (device_is_dynamic_sysbus(mc, dev)) {
1902 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
1903 SYS_BUS_DEVICE(dev));
1904 }
1905 }
1906
1907 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1908 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
1909 }
1910
1911 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
1912 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
1913 s->iommu_sys = ON_OFF_AUTO_OFF;
1914 }
1915 }
1916
virt_machine_class_init(ObjectClass * oc,const void * data)1917 static void virt_machine_class_init(ObjectClass *oc, const void *data)
1918 {
1919 MachineClass *mc = MACHINE_CLASS(oc);
1920 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1921
1922 mc->desc = "RISC-V VirtIO board";
1923 mc->init = virt_machine_init;
1924 mc->max_cpus = VIRT_CPUS_MAX;
1925 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1926 mc->block_default_type = IF_VIRTIO;
1927 mc->no_cdrom = 1;
1928 mc->pci_allow_0_address = true;
1929 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1930 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1931 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1932 mc->numa_mem_supported = true;
1933 /* platform instead of architectural choice */
1934 mc->cpu_cluster_has_numa_boundary = true;
1935 mc->default_ram_id = "riscv_virt_board.ram";
1936 assert(!mc->get_hotplug_handler);
1937 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1938
1939 hc->plug = virt_machine_device_plug_cb;
1940
1941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
1943 #ifdef CONFIG_TPM
1944 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
1945 #endif
1946
1947 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1948 virt_set_aclint);
1949 object_class_property_set_description(oc, "aclint",
1950 "(TCG only) Set on/off to "
1951 "enable/disable emulating "
1952 "ACLINT devices");
1953
1954 object_class_property_add_str(oc, "aia", virt_get_aia,
1955 virt_set_aia);
1956 object_class_property_set_description(oc, "aia",
1957 "Set type of AIA interrupt "
1958 "controller. Valid values are "
1959 "none, aplic, and aplic-imsic.");
1960
1961 object_class_property_add_str(oc, "aia-guests",
1962 virt_get_aia_guests,
1963 virt_set_aia_guests);
1964 {
1965 g_autofree char *str =
1966 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. "
1967 "Valid value should be between 0 and %d.",
1968 VIRT_IRQCHIP_MAX_GUESTS);
1969 object_class_property_set_description(oc, "aia-guests", str);
1970 }
1971
1972 object_class_property_add(oc, "acpi", "OnOffAuto",
1973 virt_get_acpi, virt_set_acpi,
1974 NULL, NULL);
1975 object_class_property_set_description(oc, "acpi",
1976 "Enable ACPI");
1977
1978 object_class_property_add(oc, "iommu-sys", "OnOffAuto",
1979 virt_get_iommu_sys, virt_set_iommu_sys,
1980 NULL, NULL);
1981 object_class_property_set_description(oc, "iommu-sys",
1982 "Enable IOMMU platform device");
1983 }
1984
1985 static const TypeInfo virt_machine_typeinfo = {
1986 .name = MACHINE_TYPE_NAME("virt"),
1987 .parent = TYPE_MACHINE,
1988 .class_init = virt_machine_class_init,
1989 .instance_init = virt_machine_instance_init,
1990 .instance_size = sizeof(RISCVVirtState),
1991 .interfaces = (const InterfaceInfo[]) {
1992 { TYPE_HOTPLUG_HANDLER },
1993 { }
1994 },
1995 };
1996
virt_machine_init_register_types(void)1997 static void virt_machine_init_register_types(void)
1998 {
1999 type_register_static(&virt_machine_typeinfo);
2000 }
2001
2002 type_init(virt_machine_init_register_types)
2003