Lines Matching +full:cpu +full:- +full:interrupt +full:- +full:controller
2 * QEMU PowerPC XIVE interrupt controller model
5 * The POWER9 processor comes with a new interrupt controller, called
6 * XIVE as "eXternal Interrupt Virtualization Engine".
11 * XIVE Interrupt Controller
12 * +------------------------------------+ IPIs
13 * | +---------+ +---------+ +--------+ | +-------+
14 * | |VC | |CQ | |PC |----> | CORES |
15 * | | esb | | | | |----> | |
16 * | | eas | | Bridge | | tctx |----> | |
18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
19 * | RAM | +------------------|-----------------+ | | |
22 * | | +--------------------v------------------------v-v-v--+ other
23 * | <--+ Power Bus +--> chips
24 * | esb | +---------+-----------------------+------------------+
26 * | end | +--|------+ |
27 * | nvt | +----+----+ | +----+----+
28 * +------+ |SC | | |SC |
30 * | PQ-bits | | | PQ-bits |
31 * | local |-+ | in VC |
32 * +---------+ +---------+
35 * SC: Source Controller (aka. IVSE)
36 * VC: Virtualization Controller (aka. IVRE)
37 * PC: Presentation Controller (aka. IVPE)
40 * PQ-bits: 2 bits source state machine (P:pending Q:queued)
45 * tctx: Thread interrupt Context
48 * The XIVE IC is composed of three sub-engines :
50 * - Interrupt Virtualization Source Engine (IVSE), or Source
51 * Controller (SC). These are found in PCI PHBs, in the PSI host
52 * bridge controller, but also inside the main controller for the
53 * core IPIs and other sub-chips (NX, CAP, NPU) of the
56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
57 * Controller (VC). Its job is to match an event source with an
60 * - Interrupt Virtualization Presentation Engine (IVPE) or
61 * Presentation Controller (PC). It maintains the interrupt context
65 * In XIVE 1.0, the sub-engines used to be referred as:
67 * SC Source Controller
68 * VC Virtualization Controller
69 * PC Presentation Controller
75 * Each of the sub-engines uses a set of tables to redirect exceptions
76 * from event sources to CPU threads.
78 * +-------+
80 * or +------>|entries|
82 * Memory | +-------+
85 * +-------------------------------------------------+
87 * Hypervisor +------+ +---+--+ +---+--+ +------+
89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+
92 * +-------------------------------------------------+
95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+
97 * IPI or --> | + v + v + v |---| + .. |-----> |
98 * HW events --> | | | | | |
99 * IVSE | IVRE | | IVPE | +------+
100 * +---------------------------------+ +-------+
104 * The IVSE have a 2-bits state machine, P for pending and Q for queued,
111 * a notification path to a CPU and an in-memory Event Queue, in which
117 * the thread interrupt context (TCTX) of each thread in a NVT table.
123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry
124 * EAT Event Assignment Table IVT Interrupt Virt. Table
130 * TCTX Thread interrupt Context
133 * Copyright (c) 2017-2024, IBM Corporation.
135 * SPDX-License-Identifier: GPL-2.0-or-later
152 #define TYPE_XIVE_NOTIFIER "xive-notifier"
165 * XIVE Interrupt Source
168 #define TYPE_XIVE_SOURCE "xive-source"
172 * XIVE Interrupt Source characteristics, which define how the ESB are
215 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE || in xive_source_esb_has_2page()
216 xsrc->esb_shift == XIVE_ESB_4K_2PAGE; in xive_source_esb_has_2page()
221 return (1ull << xsrc->esb_shift) * xsrc->nr_irqs; in xive_source_esb_len()
227 assert(srcno < xsrc->nr_irqs); in xive_source_esb_page()
228 return (1ull << xsrc->esb_shift) * srcno; in xive_source_esb_page()
237 addr += (1 << (xsrc->esb_shift - 1)); in xive_source_esb_mgmt()
244 * Each interrupt source has a 2-bit state machine which can be
245 * controlled by MMIO. P indicates that an interrupt is pending (has
247 * the interrupt has been triggered while pending.
250 * given interrupt only occurs at most once in a queue.
252 * When doing an EOI, the Q bit will indicate if the interrupt
253 * needs to be re-triggered.
272 * the PQ bits. They must be used with an 8-byte load instruction.
273 * They all return the previous state of the interrupt (atomically).
297 xsrc->status[srcno] |= status; in xive_source_set_status()
299 xsrc->status[srcno] &= ~status; in xive_source_set_status()
311 return xsrc->status[srcno] & XIVE_STATUS_ASSERTED; in xive_source_is_asserted()
319 assert(srcno < xsrc->nr_irqs); in xive_source_irq_is_lsi()
320 return test_bit(srcno, xsrc->lsi_map); in xive_source_irq_is_lsi()
325 assert(srcno < xsrc->nr_irqs); in xive_source_irq_set_lsi()
326 bitmap_set(xsrc->lsi_map, srcno, 1); in xive_source_irq_set_lsi()
332 * XIVE Thread interrupt Management (TM) context
335 #define TYPE_XIVE_TCTX "xive-tctx"
339 * XIVE Thread interrupt Management register rings :
341 * QW-0 User event-based exception state
342 * QW-1 O/S OS context for priority management, interrupt acks
343 * QW-2 Pool hypervisor pool context for virtual processors dispatched
344 * QW-3 Physical physical thread context and security context
379 #define TYPE_XIVE_ROUTER "xive-router"
428 #define TYPE_XIVE_PRESENTER "xive-presenter"
462 * XIVE Fabric (Interface between Interrupt Controller and Machine)
465 #define TYPE_XIVE_FABRIC "xive-fabric"
486 #define TYPE_XIVE_END_SOURCE "xive-end-source"
503 * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
509 * Convert a priority number to an Interrupt Pending Buffer (IPB)
510 * register, which indicates a pending interrupt at the priority
516 0 : 1 << (XIVE_PRIORITY_MAX - priority); in xive_priority_to_ipb()
525 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
526 * Interrupt Priority Register (PIPR), which contains the priority of
535 * XIVE Thread Interrupt Management Aera (TIMA)
537 * This region gives access to the registers of the thread interrupt
553 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);