Home
last modified time | relevance | path

Searched full:spi (Results 1 – 25 of 126) sorted by relevance

123456

/qemu/include/hw/ssi/
H A Dpnv_spi.h2 * QEMU PowerPC SPI model
8 * This model Supports a connection to a single SPI responder.
9 * Introduced for P10 to provide access to SPI seeproms, TPM, flash device
12 * All SPI function control is mapped into the SPI register space to enable
15 * SPI Controller has sequencer and shift engine. The SPI shift engine
18 * registers and the SPI sequencer implements the main control logic.
28 #define TYPE_PNV_SPI "pnv-spi"
34 #define TYPE_PNV_SPI_BUS "spi"
44 /* SPI object number */
67 /* SPI registers */
H A Dnpcm_pspi.h2 * Nuvoton Peripheral SPI Module
32 * @spi: The SPI bus mastered by this controller.
45 SSIBus *spi; member
H A Dsifive_spi.h2 * QEMU model of the SiFive SPI Controller
30 #define TYPE_SIFIVE_SPI "sifive.spi"
42 SSIBus *spi; member
H A Dmss-spi.h2 * Microsemi SmartFusion2 SPI
33 #define TYPE_MSS_SPI "mss-spi"
47 SSIBus *spi; member
H A Dallwinner-a10-spi.h2 * Allwinner SPI Bus Serial Interface registers definition
30 /** Size of register I/O address space used by SPI device */
38 #define TYPE_AW_A10_SPI "allwinner.spi"
H A Dnpcm7xx_fiu.h48 * @spi: The SPI bus mastered by this controller.
66 SSIBus *spi; member
H A Dibex_spi_host.h3 * QEMU model of the Ibex SPI Controller
36 #define TYPE_IBEX_SPI_HOST "ibex-spi"
40 /* SPI Registers */
H A Dxilinx_spips.h2 * Header file for the Xilinx Zynq SPI controller
78 SSIBus **spi; member
136 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
/qemu/hw/ssi/
H A Dnpcm7xx_fiu.c165 ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg)); in npcm7xx_fiu_flash_read()
169 ssi_transfer(fiu->spi, extract32(addr, 24, 8)); in npcm7xx_fiu_flash_read()
172 ssi_transfer(fiu->spi, extract32(addr, 16, 8)); in npcm7xx_fiu_flash_read()
173 ssi_transfer(fiu->spi, extract32(addr, 8, 8)); in npcm7xx_fiu_flash_read()
174 ssi_transfer(fiu->spi, extract32(addr, 0, 8)); in npcm7xx_fiu_flash_read()
187 ssi_transfer(fiu->spi, 0); in npcm7xx_fiu_flash_read()
191 value = deposit64(value, 8 * i, 8, ssi_transfer(fiu->spi, 0)); in npcm7xx_fiu_flash_read()
224 ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg)); in npcm7xx_fiu_flash_write()
228 ssi_transfer(fiu->spi, extract32(addr, 24, 8)); in npcm7xx_fiu_flash_write()
231 ssi_transfer(fiu->spi, extract32(addr, 16, 8)); in npcm7xx_fiu_flash_write()
[all …]
H A Dnpcm_pspi.c2 * Nuvoton NPCM Peripheral SPI Module (PSPI)
80 value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; in npcm_pspi_write_data()
82 value |= ssi_transfer(s->spi, extract16(data, 0, 8)); in npcm_pspi_write_data()
184 s->spi = ssi_create_bus(dev, "pspi"); in npcm_pspi_realize()
207 dc->desc = "NPCM Peripheral SPI Module"; in npcm_pspi_class_init()
H A Dxilinx_spi.c2 * QEMU model of the Xilinx SPI Controller
82 #define TYPE_XILINX_SPI "xlnx.xps-spi"
97 SSIBus *spi; member
185 rx = ssi_transfer(s->spi, tx); in spi_flush_txfifo()
346 s->spi = ssi_create_bus(dev, "spi"); in xilinx_spi_realize()
356 "xilinx-spi", R_MAX * 4); in xilinx_spi_realize()
H A Daspeed_smc.c2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
59 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
60 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
61 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
62 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
125 /* SPI dummy cycle data */
166 /* SPI controller registers and bits (AST2400) */
303 * The end address of the AST2500 spi controllers is also in aspeed_smc_flash_set_segment()
[all …]
H A Dmeson.build1 system_ss.add(when: 'CONFIG_ALLWINNER_A10_SPI', if_true: files('allwinner-a10-spi.c'))
3 system_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
/qemu/hw/intc/
H A Darm_gicv2m.c56 qemu_irq spi[GICV2M_NUM_SPI_MAX]; member
66 qemu_irq_pulse(s->spi[irq]); in gicv2m_set_irq()
115 int spi; in gicv2m_write() local
117 spi = (value & 0x3ff) - (s->base_spi + 32); in gicv2m_write()
118 if (spi >= 0 && spi < s->num_spi) { in gicv2m_write()
119 gicv2m_set_irq(s, spi); in gicv2m_write()
149 "requested base SPI %u+%u exceeds max. number 1020", in gicv2m_realize()
155 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]); in gicv2m_realize()
174 DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
175 DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
/qemu/docs/system/arm/
H A Daspeed.rst10 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
18 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
52 * Static Memory Controller (SMC or FMC) - Only SPI Flash support
53 * SPI Memory Controller
127 * ``spi-model`` to change the default SPI Flash model.
137 bigger (64M) SPI for the ``ast2500-evb`` machine, run :
141 -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f
196 boot mode of machine: SPI or eMMC. This can be useful to boot the
197 ``ast2600-evb`` machine from an eMMC device (default being SPI) or to
252 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
[all …]
/qemu/hw/arm/
H A Dmsf2-soc.c73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()
185 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { in m2sxxx_soc_realize()
189 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); in m2sxxx_soc_realize()
190 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, in m2sxxx_soc_realize()
193 /* Alias controller SPI bus to the SoC itself */ in m2sxxx_soc_realize()
194 bus_name = g_strdup_printf("spi%d", i); in m2sxxx_soc_realize()
196 OBJECT(&s->spi[i]), "spi"); in m2sxxx_soc_realize()
H A Dsabrelite.c65 * TODO: Ideally we would expose the chip select and spi bus on the in sabrelite_init()
67 * directly access the underlying spi device object. in sabrelite_init()
69 /* Add the sst25vf016b NOR FLASH memory to first SPI */ in sabrelite_init()
76 spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi"); in sabrelite_init()
H A Daspeed_ast10x0.c149 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); in aspeed_soc_ast1030_init()
150 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); in aspeed_soc_ast1030_init()
349 /* SPI */ in aspeed_soc_ast1030_realize()
351 object_property_set_link(OBJECT(&s->spi[i]), "dram", in aspeed_soc_ast1030_realize()
353 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { in aspeed_soc_ast1030_realize()
356 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, in aspeed_soc_ast1030_realize()
358 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, in aspeed_soc_ast1030_realize()
359 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); in aspeed_soc_ast1030_realize()
H A Dstm32f100_soc.c59 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f100_soc_initfn()
141 /* SPI 1 and 2 */ in stm32f100_soc_realize()
143 dev = DEVICE(&(s->spi[i])); in stm32f100_soc_realize()
144 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { in stm32f100_soc_realize()
H A Dstm32f205_soc.c76 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f205_soc_initfn()
193 /* SPI 1 and 2 */ in stm32f205_soc_realize()
195 dev = DEVICE(&(s->spi[i])); in stm32f205_soc_realize()
196 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { in stm32f205_soc_realize()
H A Daspeed_ast2400.c193 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); in aspeed_ast2400_soc_init()
194 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); in aspeed_ast2400_soc_init()
255 /* Default boot region (SPI memory or ROMs) */ in aspeed_ast2400_soc_realize()
375 /* SPI */ in aspeed_ast2400_soc_realize()
377 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { in aspeed_ast2400_soc_realize()
380 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, in aspeed_ast2400_soc_realize()
382 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, in aspeed_ast2400_soc_realize()
383 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); in aspeed_ast2400_soc_realize()
/qemu/tests/qtest/
H A Dpnv-spi-seeprom-test.c53 /* SPI transactions to SEEPROM to read from SEEPROM image */ in spi_seeprom_transaction()
67 /* SPI transactions to SEEPROM to write to SEEPROM image */ in spi_seeprom_transaction()
95 "filename=%s -device 25csm04,bus=chip0.spi.2,cs=0," in test_spi_seeprom()
105 char *tname = g_strdup_printf("pnv-xscom/spi-seeprom/%s", in main()
H A Daspeed-smc-utils.h2 * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
35 * ASPEED SPI Controller registers
40 #define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
/qemu/docs/system/riscv/
H A Dsifive_u.rst26 * 1 SD card in SPI mode
226 To start U-Boot using the ``sifive_u`` machine, prepare an SPI flash image, or
255 SPI flash image has slightly different partition offsets, and the size has to
261 image spi-nor.img {
298 Changing msel= value to 6, allows booting U-Boot from the SPI flash:
305 -drive file=/path/to/spi-nor.img,if=mtd
315 case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
320 without the needs of preparing the SPI flash or SD card images, an alternate
/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c175 SSIBus *spi; in petalogix_ml605_init() local
177 dev = qdev_new("xlnx.xps-spi"); in petalogix_ml605_init()
185 spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); in petalogix_ml605_init()
198 qdev_realize_and_unref(dev, BUS(spi), &error_fatal); in petalogix_ml605_init()

123456