1*3e62a32dSJamin Lin /* 2*3e62a32dSJamin Lin * QTest testcase for the M25P80 Flash (Using the Aspeed SPI 3*3e62a32dSJamin Lin * Controller) 4*3e62a32dSJamin Lin * 5*3e62a32dSJamin Lin * Copyright (C) 2016 IBM Corp. 6*3e62a32dSJamin Lin * 7*3e62a32dSJamin Lin * Permission is hereby granted, free of charge, to any person obtaining a copy 8*3e62a32dSJamin Lin * of this software and associated documentation files (the "Software"), to deal 9*3e62a32dSJamin Lin * in the Software without restriction, including without limitation the rights 10*3e62a32dSJamin Lin * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11*3e62a32dSJamin Lin * copies of the Software, and to permit persons to whom the Software is 12*3e62a32dSJamin Lin * furnished to do so, subject to the following conditions: 13*3e62a32dSJamin Lin * 14*3e62a32dSJamin Lin * The above copyright notice and this permission notice shall be included in 15*3e62a32dSJamin Lin * all copies or substantial portions of the Software. 16*3e62a32dSJamin Lin * 17*3e62a32dSJamin Lin * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18*3e62a32dSJamin Lin * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19*3e62a32dSJamin Lin * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20*3e62a32dSJamin Lin * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21*3e62a32dSJamin Lin * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22*3e62a32dSJamin Lin * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23*3e62a32dSJamin Lin * THE SOFTWARE. 24*3e62a32dSJamin Lin */ 25*3e62a32dSJamin Lin 26*3e62a32dSJamin Lin #ifndef TESTS_ASPEED_SMC_UTILS_H 27*3e62a32dSJamin Lin #define TESTS_ASPEED_SMC_UTILS_H 28*3e62a32dSJamin Lin 29*3e62a32dSJamin Lin #include "qemu/osdep.h" 30*3e62a32dSJamin Lin #include "qemu/bswap.h" 31*3e62a32dSJamin Lin #include "libqtest-single.h" 32*3e62a32dSJamin Lin #include "qemu/bitops.h" 33*3e62a32dSJamin Lin 34*3e62a32dSJamin Lin /* 35*3e62a32dSJamin Lin * ASPEED SPI Controller registers 36*3e62a32dSJamin Lin */ 37*3e62a32dSJamin Lin #define R_CONF 0x00 38*3e62a32dSJamin Lin #define CONF_ENABLE_W0 16 39*3e62a32dSJamin Lin #define R_CE_CTRL 0x04 40*3e62a32dSJamin Lin #define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ 41*3e62a32dSJamin Lin #define R_CTRL0 0x10 42*3e62a32dSJamin Lin #define CTRL_IO_QUAD_IO BIT(31) 43*3e62a32dSJamin Lin #define CTRL_CE_STOP_ACTIVE BIT(2) 44*3e62a32dSJamin Lin #define CTRL_READMODE 0x0 45*3e62a32dSJamin Lin #define CTRL_FREADMODE 0x1 46*3e62a32dSJamin Lin #define CTRL_WRITEMODE 0x2 47*3e62a32dSJamin Lin #define CTRL_USERMODE 0x3 48*3e62a32dSJamin Lin #define SR_WEL BIT(1) 49*3e62a32dSJamin Lin 50*3e62a32dSJamin Lin /* 51*3e62a32dSJamin Lin * Flash commands 52*3e62a32dSJamin Lin */ 53*3e62a32dSJamin Lin enum { 54*3e62a32dSJamin Lin JEDEC_READ = 0x9f, 55*3e62a32dSJamin Lin RDSR = 0x5, 56*3e62a32dSJamin Lin WRDI = 0x4, 57*3e62a32dSJamin Lin BULK_ERASE = 0xc7, 58*3e62a32dSJamin Lin READ = 0x03, 59*3e62a32dSJamin Lin PP = 0x02, 60*3e62a32dSJamin Lin WRSR = 0x1, 61*3e62a32dSJamin Lin WREN = 0x6, 62*3e62a32dSJamin Lin SRWD = 0x80, 63*3e62a32dSJamin Lin RESET_ENABLE = 0x66, 64*3e62a32dSJamin Lin RESET_MEMORY = 0x99, 65*3e62a32dSJamin Lin EN_4BYTE_ADDR = 0xB7, 66*3e62a32dSJamin Lin ERASE_SECTOR = 0xd8, 67*3e62a32dSJamin Lin }; 68*3e62a32dSJamin Lin 69*3e62a32dSJamin Lin #define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 70*3e62a32dSJamin Lin #define FLASH_PAGE_SIZE 256 71*3e62a32dSJamin Lin 72*3e62a32dSJamin Lin typedef struct AspeedSMCTestData { 73*3e62a32dSJamin Lin QTestState *s; 74*3e62a32dSJamin Lin uint64_t spi_base; 75*3e62a32dSJamin Lin uint64_t flash_base; 76*3e62a32dSJamin Lin uint32_t jedec_id; 77*3e62a32dSJamin Lin char *tmp_path; 78*3e62a32dSJamin Lin uint8_t cs; 79*3e62a32dSJamin Lin const char *node; 80*3e62a32dSJamin Lin uint32_t page_addr; 81*3e62a32dSJamin Lin } AspeedSMCTestData; 82*3e62a32dSJamin Lin 83*3e62a32dSJamin Lin void aspeed_smc_test_read_jedec(const void *data); 84*3e62a32dSJamin Lin void aspeed_smc_test_erase_sector(const void *data); 85*3e62a32dSJamin Lin void aspeed_smc_test_erase_all(const void *data); 86*3e62a32dSJamin Lin void aspeed_smc_test_write_page(const void *data); 87*3e62a32dSJamin Lin void aspeed_smc_test_read_page_mem(const void *data); 88*3e62a32dSJamin Lin void aspeed_smc_test_write_page_mem(const void *data); 89*3e62a32dSJamin Lin void aspeed_smc_test_read_status_reg(const void *data); 90*3e62a32dSJamin Lin void aspeed_smc_test_status_reg_write_protection(const void *data); 91*3e62a32dSJamin Lin void aspeed_smc_test_write_block_protect(const void *data); 92*3e62a32dSJamin Lin void aspeed_smc_test_write_block_protect_bottom_bit(const void *data); 93*3e62a32dSJamin Lin void aspeed_smc_test_write_page_qpi(const void *data); 94*3e62a32dSJamin Lin 95*3e62a32dSJamin Lin #endif /* TESTS_ASPEED_SMC_UTILS_H */ 96