129318db1SChalapathi V /* 229318db1SChalapathi V * QEMU PowerPC SPI model 329318db1SChalapathi V * 429318db1SChalapathi V * Copyright (c) 2024, IBM Corporation. 529318db1SChalapathi V * 629318db1SChalapathi V * SPDX-License-Identifier: GPL-2.0-or-later 729318db1SChalapathi V * 829318db1SChalapathi V * This model Supports a connection to a single SPI responder. 929318db1SChalapathi V * Introduced for P10 to provide access to SPI seeproms, TPM, flash device 1029318db1SChalapathi V * and an ADC controller. 11b4cb930eSChalapathi V * 12b4cb930eSChalapathi V * All SPI function control is mapped into the SPI register space to enable 13b4cb930eSChalapathi V * full control by firmware. 14b4cb930eSChalapathi V * 15b4cb930eSChalapathi V * SPI Controller has sequencer and shift engine. The SPI shift engine 16b4cb930eSChalapathi V * performs serialization and de-serialization according to the control by 17b4cb930eSChalapathi V * the sequencer and according to the setup defined in the configuration 18b4cb930eSChalapathi V * registers and the SPI sequencer implements the main control logic. 1929318db1SChalapathi V */ 2029318db1SChalapathi V 2129318db1SChalapathi V #ifndef PPC_PNV_SPI_H 2229318db1SChalapathi V #define PPC_PNV_SPI_H 2329318db1SChalapathi V 2429318db1SChalapathi V #include "hw/ssi/ssi.h" 2529318db1SChalapathi V #include "hw/sysbus.h" 2617befecdSChalapathi V #include "qemu/fifo8.h" 2729318db1SChalapathi V 2829318db1SChalapathi V #define TYPE_PNV_SPI "pnv-spi" 2929318db1SChalapathi V OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI) 3029318db1SChalapathi V 3129318db1SChalapathi V #define PNV_SPI_REG_SIZE 8 3229318db1SChalapathi V #define PNV_SPI_REGS 7 3329318db1SChalapathi V 347192d7b7SChalapathi V #define TYPE_PNV_SPI_BUS "spi" 3529318db1SChalapathi V typedef struct PnvSpi { 3629318db1SChalapathi V SysBusDevice parent_obj; 3729318db1SChalapathi V 3829318db1SChalapathi V SSIBus *ssi_bus; 3929318db1SChalapathi V qemu_irq *cs_line; 4029318db1SChalapathi V MemoryRegion xscom_spic_regs; 4117befecdSChalapathi V Fifo8 tx_fifo; 4217befecdSChalapathi V Fifo8 rx_fifo; 43*a613b9d3SChalapathi V uint8_t fail_count; /* RDR Match failure counter */ 4429318db1SChalapathi V /* SPI object number */ 4529318db1SChalapathi V uint32_t spic_num; 467192d7b7SChalapathi V uint32_t chip_id; 47b4cb930eSChalapathi V uint8_t transfer_len; 48b4cb930eSChalapathi V uint8_t responder_select; 49b4cb930eSChalapathi V /* To verify if shift_n1 happens prior to shift_n2 */ 50b4cb930eSChalapathi V bool shift_n1_done; 51b4cb930eSChalapathi V /* Loop counter for branch operation opcode Ex/Fx */ 52b4cb930eSChalapathi V uint8_t loop_counter_1; 53b4cb930eSChalapathi V uint8_t loop_counter_2; 54b4cb930eSChalapathi V /* N1/N2_bits specifies the size of the N1/N2 segment of a frame in bits.*/ 55b4cb930eSChalapathi V uint8_t N1_bits; 56b4cb930eSChalapathi V uint8_t N2_bits; 57b4cb930eSChalapathi V /* Number of bytes in a payload for the N1/N2 frame segment.*/ 58b4cb930eSChalapathi V uint8_t N1_bytes; 59b4cb930eSChalapathi V uint8_t N2_bytes; 60b4cb930eSChalapathi V /* Number of N1/N2 bytes marked for transmit */ 61b4cb930eSChalapathi V uint8_t N1_tx; 62b4cb930eSChalapathi V uint8_t N2_tx; 63b4cb930eSChalapathi V /* Number of N1/N2 bytes marked for receive */ 64b4cb930eSChalapathi V uint8_t N1_rx; 65b4cb930eSChalapathi V uint8_t N2_rx; 6629318db1SChalapathi V 6729318db1SChalapathi V /* SPI registers */ 6829318db1SChalapathi V uint64_t regs[PNV_SPI_REGS]; 6929318db1SChalapathi V uint8_t seq_op[PNV_SPI_REG_SIZE]; 7029318db1SChalapathi V uint64_t status; 7129318db1SChalapathi V } PnvSpi; 7229318db1SChalapathi V #endif /* PPC_PNV_SPI_H */ 73