xref: /qemu/hw/ssi/aspeed_smc.c (revision 6d0d9add0d98effc7045466249921a09845225ac)
17c1c69bcSCédric Le Goater /*
27c1c69bcSCédric Le Goater  * ASPEED AST2400 SMC Controller (SPI Flash Only)
37c1c69bcSCédric Le Goater  *
47c1c69bcSCédric Le Goater  * Copyright (C) 2016 IBM Corp.
57c1c69bcSCédric Le Goater  *
67c1c69bcSCédric Le Goater  * Permission is hereby granted, free of charge, to any person obtaining a copy
77c1c69bcSCédric Le Goater  * of this software and associated documentation files (the "Software"), to deal
87c1c69bcSCédric Le Goater  * in the Software without restriction, including without limitation the rights
97c1c69bcSCédric Le Goater  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
107c1c69bcSCédric Le Goater  * copies of the Software, and to permit persons to whom the Software is
117c1c69bcSCédric Le Goater  * furnished to do so, subject to the following conditions:
127c1c69bcSCédric Le Goater  *
137c1c69bcSCédric Le Goater  * The above copyright notice and this permission notice shall be included in
147c1c69bcSCédric Le Goater  * all copies or substantial portions of the Software.
157c1c69bcSCédric Le Goater  *
167c1c69bcSCédric Le Goater  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
177c1c69bcSCédric Le Goater  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
187c1c69bcSCédric Le Goater  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
197c1c69bcSCédric Le Goater  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
207c1c69bcSCédric Le Goater  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
217c1c69bcSCédric Le Goater  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
227c1c69bcSCédric Le Goater  * THE SOFTWARE.
237c1c69bcSCédric Le Goater  */
247c1c69bcSCédric Le Goater 
257c1c69bcSCédric Le Goater #include "qemu/osdep.h"
26a7538ca0SCédric Le Goater #include "hw/block/flash.h"
277c1c69bcSCédric Le Goater #include "hw/sysbus.h"
28d6454270SMarkus Armbruster #include "migration/vmstate.h"
297c1c69bcSCédric Le Goater #include "qemu/log.h"
300b8fa32fSMarkus Armbruster #include "qemu/module.h"
31d6e3f50aSPhilippe Mathieu-Daudé #include "qemu/error-report.h"
32c4e1f0b4SCédric Le Goater #include "qapi/error.h"
33bcaa8dddSCédric Le Goater #include "qemu/units.h"
34bd6ce9a6SCédric Le Goater #include "trace.h"
357c1c69bcSCédric Le Goater 
3664552b6bSMarkus Armbruster #include "hw/irq.h"
37a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h"
387c1c69bcSCédric Le Goater #include "hw/ssi/aspeed_smc.h"
397c1c69bcSCédric Le Goater 
407c1c69bcSCédric Le Goater /* CE Type Setting Register */
417c1c69bcSCédric Le Goater #define R_CONF            (0x00 / 4)
427c1c69bcSCédric Le Goater #define   CONF_LEGACY_DISABLE  (1 << 31)
437c1c69bcSCédric Le Goater #define   CONF_ENABLE_W4       20
447c1c69bcSCédric Le Goater #define   CONF_ENABLE_W3       19
457c1c69bcSCédric Le Goater #define   CONF_ENABLE_W2       18
467c1c69bcSCédric Le Goater #define   CONF_ENABLE_W1       17
477c1c69bcSCédric Le Goater #define   CONF_ENABLE_W0       16
480707b34dSCédric Le Goater #define   CONF_FLASH_TYPE4     8
490707b34dSCédric Le Goater #define   CONF_FLASH_TYPE3     6
500707b34dSCédric Le Goater #define   CONF_FLASH_TYPE2     4
510707b34dSCédric Le Goater #define   CONF_FLASH_TYPE1     2
520707b34dSCédric Le Goater #define   CONF_FLASH_TYPE0     0
530707b34dSCédric Le Goater #define      CONF_FLASH_TYPE_NOR   0x0
540707b34dSCédric Le Goater #define      CONF_FLASH_TYPE_NAND  0x1
55bcaa8dddSCédric Le Goater #define      CONF_FLASH_TYPE_SPI   0x2 /* AST2600 is SPI only */
567c1c69bcSCédric Le Goater 
577c1c69bcSCédric Le Goater /* CE Control Register */
587c1c69bcSCédric Le Goater #define R_CE_CTRL            (0x04 / 4)
597c1c69bcSCédric Le Goater #define   CTRL_EXTENDED4       4  /* 32 bit addressing for SPI */
607c1c69bcSCédric Le Goater #define   CTRL_EXTENDED3       3  /* 32 bit addressing for SPI */
617c1c69bcSCédric Le Goater #define   CTRL_EXTENDED2       2  /* 32 bit addressing for SPI */
627c1c69bcSCédric Le Goater #define   CTRL_EXTENDED1       1  /* 32 bit addressing for SPI */
637c1c69bcSCédric Le Goater #define   CTRL_EXTENDED0       0  /* 32 bit addressing for SPI */
647c1c69bcSCédric Le Goater 
657c1c69bcSCédric Le Goater /* Interrupt Control and Status Register */
667c1c69bcSCédric Le Goater #define R_INTR_CTRL       (0x08 / 4)
677c1c69bcSCédric Le Goater #define   INTR_CTRL_DMA_STATUS            (1 << 11)
687c1c69bcSCédric Le Goater #define   INTR_CTRL_CMD_ABORT_STATUS      (1 << 10)
697c1c69bcSCédric Le Goater #define   INTR_CTRL_WRITE_PROTECT_STATUS  (1 << 9)
707c1c69bcSCédric Le Goater #define   INTR_CTRL_DMA_EN                (1 << 3)
717c1c69bcSCédric Le Goater #define   INTR_CTRL_CMD_ABORT_EN          (1 << 2)
727c1c69bcSCédric Le Goater #define   INTR_CTRL_WRITE_PROTECT_EN      (1 << 1)
737c1c69bcSCédric Le Goater 
74af453a5eSCédric Le Goater /* Command Control Register */
75af453a5eSCédric Le Goater #define R_CE_CMD_CTRL      (0x0C / 4)
76af453a5eSCédric Le Goater #define   CTRL_ADDR_BYTE0_DISABLE_SHIFT       4
77af453a5eSCédric Le Goater #define   CTRL_DATA_BYTE0_DISABLE_SHIFT       0
78af453a5eSCédric Le Goater 
79af453a5eSCédric Le Goater #define aspeed_smc_addr_byte_enabled(s, i)                               \
80af453a5eSCédric Le Goater     (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
81af453a5eSCédric Le Goater #define aspeed_smc_data_byte_enabled(s, i)                               \
82af453a5eSCédric Le Goater     (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
83af453a5eSCédric Le Goater 
847c1c69bcSCédric Le Goater /* CEx Control Register */
857c1c69bcSCédric Le Goater #define R_CTRL0           (0x10 / 4)
86bcaa8dddSCédric Le Goater #define   CTRL_IO_QPI              (1 << 31)
87bcaa8dddSCédric Le Goater #define   CTRL_IO_QUAD_DATA        (1 << 30)
880721309eSCédric Le Goater #define   CTRL_IO_DUAL_DATA        (1 << 29)
890721309eSCédric Le Goater #define   CTRL_IO_DUAL_ADDR_DATA   (1 << 28) /* Includes dummies */
90bcaa8dddSCédric Le Goater #define   CTRL_IO_QUAD_ADDR_DATA   (1 << 28) /* Includes dummies */
917c1c69bcSCédric Le Goater #define   CTRL_CMD_SHIFT           16
927c1c69bcSCédric Le Goater #define   CTRL_CMD_MASK            0xff
93ac2810deSCédric Le Goater #define   CTRL_DUMMY_HIGH_SHIFT    14
94fcdf2c59SCédric Le Goater #define   CTRL_AST2400_SPI_4BYTE   (1 << 13)
950d72c717SCédric Le Goater #define CE_CTRL_CLOCK_FREQ_SHIFT   8
960d72c717SCédric Le Goater #define CE_CTRL_CLOCK_FREQ_MASK    0xf
970d72c717SCédric Le Goater #define CE_CTRL_CLOCK_FREQ(div)                                         \
980d72c717SCédric Le Goater     (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
99ac2810deSCédric Le Goater #define   CTRL_DUMMY_LOW_SHIFT     6 /* 2 bits [7:6] */
1007c1c69bcSCédric Le Goater #define   CTRL_CE_STOP_ACTIVE      (1 << 2)
1017c1c69bcSCédric Le Goater #define   CTRL_CMD_MODE_MASK       0x3
1027c1c69bcSCédric Le Goater #define     CTRL_READMODE          0x0
1037c1c69bcSCédric Le Goater #define     CTRL_FREADMODE         0x1
1047c1c69bcSCédric Le Goater #define     CTRL_WRITEMODE         0x2
1057c1c69bcSCédric Le Goater #define     CTRL_USERMODE          0x3
1067c1c69bcSCédric Le Goater #define R_CTRL1           (0x14 / 4)
1077c1c69bcSCédric Le Goater #define R_CTRL2           (0x18 / 4)
1087c1c69bcSCédric Le Goater #define R_CTRL3           (0x1C / 4)
1097c1c69bcSCédric Le Goater #define R_CTRL4           (0x20 / 4)
1107c1c69bcSCédric Le Goater 
1117c1c69bcSCédric Le Goater /* CEx Segment Address Register */
1127c1c69bcSCédric Le Goater #define R_SEG_ADDR0       (0x30 / 4)
113a03cb1daSCédric Le Goater #define   SEG_END_SHIFT        24   /* 8MB units */
114a03cb1daSCédric Le Goater #define   SEG_END_MASK         0xff
1157c1c69bcSCédric Le Goater #define   SEG_START_SHIFT      16   /* address bit [A29-A23] */
116a03cb1daSCédric Le Goater #define   SEG_START_MASK       0xff
1177c1c69bcSCédric Le Goater #define R_SEG_ADDR1       (0x34 / 4)
1187c1c69bcSCédric Le Goater #define R_SEG_ADDR2       (0x38 / 4)
1197c1c69bcSCédric Le Goater #define R_SEG_ADDR3       (0x3C / 4)
1207c1c69bcSCédric Le Goater #define R_SEG_ADDR4       (0x40 / 4)
1217c1c69bcSCédric Le Goater 
1227c1c69bcSCédric Le Goater /* Misc Control Register #1 */
1237c1c69bcSCédric Le Goater #define R_MISC_CTRL1      (0x50 / 4)
1247c1c69bcSCédric Le Goater 
1259149af2aSCédric Le Goater /* SPI dummy cycle data */
1269149af2aSCédric Le Goater #define R_DUMMY_DATA      (0x54 / 4)
1277c1c69bcSCédric Le Goater 
12845a904afSCédric Le Goater /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */
12945a904afSCédric Le Goater #define R_FMC_WDT2_CTRL   (0x64 / 4)
13045a904afSCédric Le Goater #define   FMC_WDT2_CTRL_ALT_BOOT_MODE    BIT(6) /* O: 2 chips 1: 1 chip */
13145a904afSCédric Le Goater #define   FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5)
13245a904afSCédric Le Goater #define   FMC_WDT2_CTRL_BOOT_SOURCE      BIT(4) /* O: primary 1: alternate */
13345a904afSCédric Le Goater #define   FMC_WDT2_CTRL_EN               BIT(0)
13445a904afSCédric Le Goater 
1356330be8dSJamin Lin /* DMA DRAM Side Address High Part (AST2700) */
1366330be8dSJamin Lin #define R_DMA_DRAM_ADDR_HIGH   (0x7c / 4)
1376330be8dSJamin Lin 
1387c1c69bcSCédric Le Goater /* DMA Control/Status Register */
1397c1c69bcSCédric Le Goater #define R_DMA_CTRL        (0x80 / 4)
1401769a70eSCédric Le Goater #define   DMA_CTRL_REQUEST      (1 << 31)
1411769a70eSCédric Le Goater #define   DMA_CTRL_GRANT        (1 << 30)
1427c1c69bcSCédric Le Goater #define   DMA_CTRL_DELAY_MASK   0xf
1437c1c69bcSCédric Le Goater #define   DMA_CTRL_DELAY_SHIFT  8
1447c1c69bcSCédric Le Goater #define   DMA_CTRL_FREQ_MASK    0xf
1457c1c69bcSCédric Le Goater #define   DMA_CTRL_FREQ_SHIFT   4
1460d72c717SCédric Le Goater #define   DMA_CTRL_CALIB        (1 << 3)
1477c1c69bcSCédric Le Goater #define   DMA_CTRL_CKSUM        (1 << 2)
148c4e1f0b4SCédric Le Goater #define   DMA_CTRL_WRITE        (1 << 1)
149c4e1f0b4SCédric Le Goater #define   DMA_CTRL_ENABLE       (1 << 0)
1507c1c69bcSCédric Le Goater 
1517c1c69bcSCédric Le Goater /* DMA Flash Side Address */
1527c1c69bcSCédric Le Goater #define R_DMA_FLASH_ADDR  (0x84 / 4)
1537c1c69bcSCédric Le Goater 
1547c1c69bcSCédric Le Goater /* DMA DRAM Side Address */
1557c1c69bcSCédric Le Goater #define R_DMA_DRAM_ADDR   (0x88 / 4)
1567c1c69bcSCédric Le Goater 
1577c1c69bcSCédric Le Goater /* DMA Length Register */
1587c1c69bcSCédric Le Goater #define R_DMA_LEN         (0x8C / 4)
1597c1c69bcSCédric Le Goater 
1607c1c69bcSCédric Le Goater /* Checksum Calculation Result */
1617c1c69bcSCédric Le Goater #define R_DMA_CHECKSUM    (0x90 / 4)
1627c1c69bcSCédric Le Goater 
163f286f04cSCédric Le Goater /* Read Timing Compensation Register */
1647c1c69bcSCédric Le Goater #define R_TIMINGS         (0x94 / 4)
1657c1c69bcSCédric Le Goater 
166bcaa8dddSCédric Le Goater /* SPI controller registers and bits (AST2400) */
1677c1c69bcSCédric Le Goater #define R_SPI_CONF        (0x00 / 4)
1687c1c69bcSCédric Le Goater #define   SPI_CONF_ENABLE_W0   0
1697c1c69bcSCédric Le Goater #define R_SPI_CTRL0       (0x4 / 4)
1707c1c69bcSCédric Le Goater #define R_SPI_MISC_CTRL   (0x10 / 4)
1717c1c69bcSCédric Le Goater #define R_SPI_TIMINGS     (0x14 / 4)
1727c1c69bcSCédric Le Goater 
173087b57c9SCédric Le Goater #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
174087b57c9SCédric Le Goater #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
175087b57c9SCédric Le Goater 
176c4e1f0b4SCédric Le Goater /*
177c4e1f0b4SCédric Le Goater  * DMA DRAM addresses should be 4 bytes aligned and the valid address
178c4e1f0b4SCédric Le Goater  * range is 0x40000000 - 0x5FFFFFFF (AST2400)
179c4e1f0b4SCédric Le Goater  *          0x80000000 - 0xBFFFFFFF (AST2500)
180c4e1f0b4SCédric Le Goater  *
181c4e1f0b4SCédric Le Goater  * DMA flash addresses should be 4 bytes aligned and the valid address
182c4e1f0b4SCédric Le Goater  * range is 0x20000000 - 0x2FFFFFFF.
183c4e1f0b4SCédric Le Goater  *
1843a6c0f0eSJamin Lin  * DMA length is from 4 bytes to 32MB (AST2500)
185c4e1f0b4SCédric Le Goater  *   0: 4 bytes
1863a6c0f0eSJamin Lin  *   0x1FFFFFC: 32M bytes
1873a6c0f0eSJamin Lin  *
188bdb3748dSJamin Lin  * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700)
1893a6c0f0eSJamin Lin  *   0: 1 byte
1903a6c0f0eSJamin Lin  *   0x1FFFFFF: 32M bytes
191c4e1f0b4SCédric Le Goater  */
19230b6852cSCédric Le Goater #define DMA_DRAM_ADDR(asc, val)   ((val) & (asc)->dma_dram_mask)
1936330be8dSJamin Lin #define DMA_DRAM_ADDR_HIGH(val)   ((val) & 0xf)
19430b6852cSCédric Le Goater #define DMA_FLASH_ADDR(asc, val)  ((val) & (asc)->dma_flash_mask)
1953a6c0f0eSJamin Lin #define DMA_LENGTH(val)         ((val) & 0x01FFFFFF)
196c4e1f0b4SCédric Le Goater 
197fcdf2c59SCédric Le Goater /* Flash opcodes. */
198fcdf2c59SCédric Le Goater #define SPI_OP_READ       0x03    /* Read data bytes (low frequency) */
199fcdf2c59SCédric Le Goater 
200f95c4bffSCédric Le Goater #define SNOOP_OFF         0xFF
201f95c4bffSCédric Le Goater #define SNOOP_START       0x0
202f95c4bffSCédric Le Goater 
203924ed163SCédric Le Goater /*
2045ade579bSPhilippe Mathieu-Daudé  * Default segments mapping addresses and size for each peripheral per
205924ed163SCédric Le Goater  * controller. These can be changed when board is initialized with the
206a03cb1daSCédric Le Goater  * Segment Address Registers.
207924ed163SCédric Le Goater  */
20830b6852cSCédric Le Goater static const AspeedSegments aspeed_2500_spi1_segments[];
20930b6852cSCédric Le Goater static const AspeedSegments aspeed_2500_spi2_segments[];
2101769a70eSCédric Le Goater 
2111c5ee69dSCédric Le Goater #define ASPEED_SMC_FEATURE_DMA       0x1
2121769a70eSCédric Le Goater #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
21345a904afSCédric Le Goater #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
2146330be8dSJamin Lin #define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08
2151c5ee69dSCédric Le Goater 
aspeed_smc_has_dma(const AspeedSMCClass * asc)21630b6852cSCédric Le Goater static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)
2171c5ee69dSCédric Le Goater {
21830b6852cSCédric Le Goater     return !!(asc->features & ASPEED_SMC_FEATURE_DMA);
2191c5ee69dSCédric Le Goater }
220bcaa8dddSCédric Le Goater 
aspeed_smc_has_wdt_control(const AspeedSMCClass * asc)22130b6852cSCédric Le Goater static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc)
22245a904afSCédric Le Goater {
22330b6852cSCédric Le Goater     return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);
224bcaa8dddSCédric Le Goater }
225bcaa8dddSCédric Le Goater 
aspeed_smc_has_dma64(const AspeedSMCClass * asc)2266330be8dSJamin Lin static inline bool aspeed_smc_has_dma64(const AspeedSMCClass *asc)
2276330be8dSJamin Lin {
2286330be8dSJamin Lin     return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH);
2296330be8dSJamin Lin }
2306330be8dSJamin Lin 
23132c54bd0SCédric Le Goater #define aspeed_smc_error(fmt, ...)                                      \
23232c54bd0SCédric Le Goater     qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)
23332c54bd0SCédric Le Goater 
aspeed_smc_flash_overlap(const AspeedSMCState * s,const AspeedSegments * new,int cs)234a03cb1daSCédric Le Goater static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
235a03cb1daSCédric Le Goater                                      const AspeedSegments *new,
236a03cb1daSCédric Le Goater                                      int cs)
237a03cb1daSCédric Le Goater {
23830b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
239a03cb1daSCédric Le Goater     AspeedSegments seg;
240a03cb1daSCédric Le Goater     int i;
241a03cb1daSCédric Le Goater 
242ae945a00SCédric Le Goater     for (i = 0; i < asc->cs_num_max; i++) {
243a03cb1daSCédric Le Goater         if (i == cs) {
244a03cb1daSCédric Le Goater             continue;
245a03cb1daSCédric Le Goater         }
246a03cb1daSCédric Le Goater 
24730b6852cSCédric Le Goater         asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
248a03cb1daSCédric Le Goater 
249a03cb1daSCédric Le Goater         if (new->addr + new->size > seg.addr &&
250a03cb1daSCédric Le Goater             new->addr < seg.addr + seg.size) {
25132c54bd0SCédric Le Goater             aspeed_smc_error("new segment CS%d [ 0x%"
252a03cb1daSCédric Le Goater                              HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
25332c54bd0SCédric Le Goater                              "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
25432c54bd0SCédric Le Goater                              cs, new->addr, new->addr + new->size,
255a03cb1daSCédric Le Goater                              i, seg.addr, seg.addr + seg.size);
256a03cb1daSCédric Le Goater             return true;
257a03cb1daSCédric Le Goater         }
258a03cb1daSCédric Le Goater     }
259a03cb1daSCédric Le Goater     return false;
260a03cb1daSCédric Le Goater }
261a03cb1daSCédric Le Goater 
aspeed_smc_flash_set_segment_region(AspeedSMCState * s,int cs,uint64_t regval)262673b1f86SCédric Le Goater static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
263673b1f86SCédric Le Goater                                                 uint64_t regval)
264673b1f86SCédric Le Goater {
26530b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
266673b1f86SCédric Le Goater     AspeedSMCFlash *fl = &s->flashes[cs];
267673b1f86SCédric Le Goater     AspeedSegments seg;
268673b1f86SCédric Le Goater 
26930b6852cSCédric Le Goater     asc->reg_to_segment(s, regval, &seg);
270673b1f86SCédric Le Goater 
271673b1f86SCédric Le Goater     memory_region_transaction_begin();
272673b1f86SCédric Le Goater     memory_region_set_size(&fl->mmio, seg.size);
27330b6852cSCédric Le Goater     memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base);
2742175eacfSCédric Le Goater     memory_region_set_enabled(&fl->mmio, !!seg.size);
275673b1f86SCédric Le Goater     memory_region_transaction_commit();
276673b1f86SCédric Le Goater 
2777c8d2fc4SCédric Le Goater     if (asc->segment_addr_mask) {
2787c8d2fc4SCédric Le Goater         regval &= asc->segment_addr_mask;
2797c8d2fc4SCédric Le Goater     }
2807c8d2fc4SCédric Le Goater 
281673b1f86SCédric Le Goater     s->regs[R_SEG_ADDR0 + cs] = regval;
282673b1f86SCédric Le Goater }
283673b1f86SCédric Le Goater 
aspeed_smc_flash_set_segment(AspeedSMCState * s,int cs,uint64_t new)284a03cb1daSCédric Le Goater static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
285a03cb1daSCédric Le Goater                                          uint64_t new)
286a03cb1daSCédric Le Goater {
28730b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
288a03cb1daSCédric Le Goater     AspeedSegments seg;
289a03cb1daSCédric Le Goater 
29030b6852cSCédric Le Goater     asc->reg_to_segment(s, new, &seg);
291a03cb1daSCédric Le Goater 
292bd6ce9a6SCédric Le Goater     trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
293bd6ce9a6SCédric Le Goater 
294a03cb1daSCédric Le Goater     /* The start address of CS0 is read-only */
29530b6852cSCédric Le Goater     if (cs == 0 && seg.addr != asc->flash_window_base) {
29632c54bd0SCédric Le Goater         aspeed_smc_error("Tried to change CS0 start address to 0x%"
29732c54bd0SCédric Le Goater                          HWADDR_PRIx, seg.addr);
29830b6852cSCédric Le Goater         seg.addr = asc->flash_window_base;
29930b6852cSCédric Le Goater         new = asc->segment_to_reg(s, &seg);
300a03cb1daSCédric Le Goater     }
301a03cb1daSCédric Le Goater 
302a03cb1daSCédric Le Goater     /*
303a03cb1daSCédric Le Goater      * The end address of the AST2500 spi controllers is also
304a03cb1daSCédric Le Goater      * read-only.
305a03cb1daSCédric Le Goater      */
30630b6852cSCédric Le Goater     if ((asc->segments == aspeed_2500_spi1_segments ||
30730b6852cSCédric Le Goater          asc->segments == aspeed_2500_spi2_segments) &&
308ae945a00SCédric Le Goater         cs == asc->cs_num_max &&
30930b6852cSCédric Le Goater         seg.addr + seg.size != asc->segments[cs].addr +
31030b6852cSCédric Le Goater         asc->segments[cs].size) {
31132c54bd0SCédric Le Goater         aspeed_smc_error("Tried to change CS%d end address to 0x%"
31232c54bd0SCédric Le Goater                          HWADDR_PRIx, cs, seg.addr + seg.size);
31330b6852cSCédric Le Goater         seg.size = asc->segments[cs].addr + asc->segments[cs].size -
3140584d3c3SCédric Le Goater             seg.addr;
31530b6852cSCédric Le Goater         new = asc->segment_to_reg(s, &seg);
316a03cb1daSCédric Le Goater     }
317a03cb1daSCédric Le Goater 
318a03cb1daSCédric Le Goater     /* Keep the segment in the overall flash window */
3192175eacfSCédric Le Goater     if (seg.size &&
32030b6852cSCédric Le Goater         (seg.addr + seg.size <= asc->flash_window_base ||
32130b6852cSCédric Le Goater          seg.addr > asc->flash_window_base + asc->flash_window_size)) {
32232c54bd0SCédric Le Goater         aspeed_smc_error("new segment for CS%d is invalid : "
32332c54bd0SCédric Le Goater                          "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
32432c54bd0SCédric Le Goater                          cs, seg.addr, seg.addr + seg.size);
325a03cb1daSCédric Le Goater         return;
326a03cb1daSCédric Le Goater     }
327a03cb1daSCédric Le Goater 
328a03cb1daSCédric Le Goater     /* Check start address vs. alignment */
3290584d3c3SCédric Le Goater     if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
33032c54bd0SCédric Le Goater         aspeed_smc_error("new segment for CS%d is not "
33132c54bd0SCédric Le Goater                          "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
33232c54bd0SCédric Le Goater                          cs, seg.addr, seg.addr + seg.size);
333a03cb1daSCédric Le Goater     }
334a03cb1daSCédric Le Goater 
3350584d3c3SCédric Le Goater     /* And segments should not overlap (in the specs) */
3360584d3c3SCédric Le Goater     aspeed_smc_flash_overlap(s, &seg, cs);
337a03cb1daSCédric Le Goater 
338a03cb1daSCédric Le Goater     /* All should be fine now to move the region */
339673b1f86SCédric Le Goater     aspeed_smc_flash_set_segment_region(s, cs, new);
340a03cb1daSCédric Le Goater }
341a03cb1daSCédric Le Goater 
aspeed_smc_flash_default_read(void * opaque,hwaddr addr,unsigned size)342924ed163SCédric Le Goater static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
343924ed163SCédric Le Goater                                               unsigned size)
344924ed163SCédric Le Goater {
345c1402ea1SCédric Le Goater     aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size);
346924ed163SCédric Le Goater     return 0;
347924ed163SCédric Le Goater }
348924ed163SCédric Le Goater 
aspeed_smc_flash_default_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)349924ed163SCédric Le Goater static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
350924ed163SCédric Le Goater                                            uint64_t data, unsigned size)
351924ed163SCédric Le Goater {
35232c54bd0SCédric Le Goater     aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64,
35332c54bd0SCédric Le Goater                      addr, size, data);
354924ed163SCédric Le Goater }
355924ed163SCédric Le Goater 
356924ed163SCédric Le Goater static const MemoryRegionOps aspeed_smc_flash_default_ops = {
357924ed163SCédric Le Goater     .read = aspeed_smc_flash_default_read,
358924ed163SCédric Le Goater     .write = aspeed_smc_flash_default_write,
359924ed163SCédric Le Goater     .endianness = DEVICE_LITTLE_ENDIAN,
360924ed163SCédric Le Goater     .valid = {
361924ed163SCédric Le Goater         .min_access_size = 1,
362*47cdaa46SJoe Komlodi         .max_access_size = 8,
363924ed163SCédric Le Goater     },
364924ed163SCédric Le Goater };
365924ed163SCédric Le Goater 
aspeed_smc_flash_mode(const AspeedSMCFlash * fl)366f248a9dbSCédric Le Goater static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
367924ed163SCédric Le Goater {
368f248a9dbSCédric Le Goater     const AspeedSMCState *s = fl->controller;
369f248a9dbSCédric Le Goater 
37010f915e4SCédric Le Goater     return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK;
371924ed163SCédric Le Goater }
372924ed163SCédric Le Goater 
aspeed_smc_is_writable(const AspeedSMCFlash * fl)373f248a9dbSCédric Le Goater static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
374924ed163SCédric Le Goater {
375f248a9dbSCédric Le Goater     const AspeedSMCState *s = fl->controller;
376f248a9dbSCédric Le Goater 
37710f915e4SCédric Le Goater     return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs));
378924ed163SCédric Le Goater }
379924ed163SCédric Le Goater 
aspeed_smc_flash_cmd(const AspeedSMCFlash * fl)380fcdf2c59SCédric Le Goater static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
381fcdf2c59SCédric Le Goater {
382fcdf2c59SCédric Le Goater     const AspeedSMCState *s = fl->controller;
38310f915e4SCédric Le Goater     int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
384fcdf2c59SCédric Le Goater 
385bcaa8dddSCédric Le Goater     /*
386bcaa8dddSCédric Le Goater      * In read mode, the default SPI command is READ (0x3). In other
387bcaa8dddSCédric Le Goater      * modes, the command should necessarily be defined
388bcaa8dddSCédric Le Goater      *
389bcaa8dddSCédric Le Goater      * TODO: add support for READ4 (0x13) on AST2600
390bcaa8dddSCédric Le Goater      */
391fcdf2c59SCédric Le Goater     if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
392fcdf2c59SCédric Le Goater         cmd = SPI_OP_READ;
393fcdf2c59SCédric Le Goater     }
394fcdf2c59SCédric Le Goater 
395fcdf2c59SCédric Le Goater     if (!cmd) {
39632c54bd0SCédric Le Goater         aspeed_smc_error("no command defined for mode %d",
39732c54bd0SCédric Le Goater                          aspeed_smc_flash_mode(fl));
398fcdf2c59SCédric Le Goater     }
399fcdf2c59SCédric Le Goater 
400fcdf2c59SCédric Le Goater     return cmd;
401fcdf2c59SCédric Le Goater }
402fcdf2c59SCédric Le Goater 
aspeed_smc_flash_addr_width(const AspeedSMCFlash * fl)403a779e37cSCédric Le Goater static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
404fcdf2c59SCédric Le Goater {
405fcdf2c59SCédric Le Goater     const AspeedSMCState *s = fl->controller;
406b84a9482SCédric Le Goater     AspeedSMCClass *asc = fl->asc;
407fcdf2c59SCédric Le Goater 
408a779e37cSCédric Le Goater     if (asc->addr_width) {
409a779e37cSCédric Le Goater         return asc->addr_width(s);
410fcdf2c59SCédric Le Goater     } else {
411a779e37cSCédric Le Goater         return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3;
412fcdf2c59SCédric Le Goater     }
413fcdf2c59SCédric Le Goater }
414fcdf2c59SCédric Le Goater 
aspeed_smc_flash_do_select(AspeedSMCFlash * fl,bool unselect)415e7e741caSCédric Le Goater static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
416fcdf2c59SCédric Le Goater {
417e7e741caSCédric Le Goater     AspeedSMCState *s = fl->controller;
418fcdf2c59SCédric Le Goater 
41910f915e4SCédric Le Goater     trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : "");
42005d501a1SJamin Lin     s->unselect = unselect;
42110f915e4SCédric Le Goater     qemu_set_irq(s->cs_lines[fl->cs], unselect);
422fcdf2c59SCédric Le Goater }
423fcdf2c59SCédric Le Goater 
aspeed_smc_flash_select(AspeedSMCFlash * fl)424fcdf2c59SCédric Le Goater static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
425fcdf2c59SCédric Le Goater {
426e7e741caSCédric Le Goater     aspeed_smc_flash_do_select(fl, false);
427fcdf2c59SCédric Le Goater }
428fcdf2c59SCédric Le Goater 
aspeed_smc_flash_unselect(AspeedSMCFlash * fl)429fcdf2c59SCédric Le Goater static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
430fcdf2c59SCédric Le Goater {
431e7e741caSCédric Le Goater     aspeed_smc_flash_do_select(fl, true);
432fcdf2c59SCédric Le Goater }
433fcdf2c59SCédric Le Goater 
aspeed_smc_check_segment_addr(const AspeedSMCFlash * fl,uint32_t addr)434fcdf2c59SCédric Le Goater static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
435fcdf2c59SCédric Le Goater                                               uint32_t addr)
436fcdf2c59SCédric Le Goater {
437fcdf2c59SCédric Le Goater     const AspeedSMCState *s = fl->controller;
438b84a9482SCédric Le Goater     AspeedSMCClass *asc = fl->asc;
439fcdf2c59SCédric Le Goater     AspeedSegments seg;
440fcdf2c59SCédric Le Goater 
44110f915e4SCédric Le Goater     asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
442b4cc583fSCédric Le Goater     if ((addr % seg.size) != addr) {
44332c54bd0SCédric Le Goater         aspeed_smc_error("invalid address 0x%08x for CS%d segment : "
44432c54bd0SCédric Le Goater                          "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
44510f915e4SCédric Le Goater                          addr, fl->cs, seg.addr, seg.addr + seg.size);
446b4cc583fSCédric Le Goater         addr %= seg.size;
447fcdf2c59SCédric Le Goater     }
448fcdf2c59SCédric Le Goater 
449fcdf2c59SCédric Le Goater     return addr;
450fcdf2c59SCédric Le Goater }
451fcdf2c59SCédric Le Goater 
aspeed_smc_flash_dummies(const AspeedSMCFlash * fl)452ac2810deSCédric Le Goater static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
453ac2810deSCédric Le Goater {
454ac2810deSCédric Le Goater     const AspeedSMCState *s = fl->controller;
45510f915e4SCédric Le Goater     uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs];
456ac2810deSCédric Le Goater     uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
457ac2810deSCédric Le Goater     uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
4580721309eSCédric Le Goater     uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
459ac2810deSCédric Le Goater 
4600721309eSCédric Le Goater     if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
4610721309eSCédric Le Goater         dummies /= 2;
4620721309eSCédric Le Goater     }
4630721309eSCédric Le Goater 
4640721309eSCédric Le Goater     return dummies;
465ac2810deSCédric Le Goater }
466ac2810deSCédric Le Goater 
aspeed_smc_flash_setup(AspeedSMCFlash * fl,uint32_t addr)46796c4be95SCédric Le Goater static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
468fcdf2c59SCédric Le Goater {
469fcdf2c59SCédric Le Goater     const AspeedSMCState *s = fl->controller;
470fcdf2c59SCédric Le Goater     uint8_t cmd = aspeed_smc_flash_cmd(fl);
471a779e37cSCédric Le Goater     int i = aspeed_smc_flash_addr_width(fl);
472fcdf2c59SCédric Le Goater 
473fcdf2c59SCédric Le Goater     /* Flash access can not exceed CS segment */
474fcdf2c59SCédric Le Goater     addr = aspeed_smc_check_segment_addr(fl, addr);
475fcdf2c59SCédric Le Goater 
476fcdf2c59SCédric Le Goater     ssi_transfer(s->spi, cmd);
477af453a5eSCédric Le Goater     while (i--) {
478af453a5eSCédric Le Goater         if (aspeed_smc_addr_byte_enabled(s, i)) {
479af453a5eSCédric Le Goater             ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
480fcdf2c59SCédric Le Goater         }
481af453a5eSCédric Le Goater     }
48296c4be95SCédric Le Goater 
48396c4be95SCédric Le Goater     /*
48496c4be95SCédric Le Goater      * Use fake transfers to model dummy bytes. The value should
48596c4be95SCédric Le Goater      * be configured to some non-zero value in fast read mode and
48696c4be95SCédric Le Goater      * zero in read mode. But, as the HW allows inconsistent
48796c4be95SCédric Le Goater      * settings, let's check for fast read mode.
48896c4be95SCédric Le Goater      */
48996c4be95SCédric Le Goater     if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
49096c4be95SCédric Le Goater         for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
4919149af2aSCédric Le Goater             ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
49296c4be95SCédric Le Goater         }
49396c4be95SCédric Le Goater     }
494fcdf2c59SCédric Le Goater }
495fcdf2c59SCédric Le Goater 
aspeed_smc_flash_read(void * opaque,hwaddr addr,unsigned size)496924ed163SCédric Le Goater static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
497924ed163SCédric Le Goater {
498924ed163SCédric Le Goater     AspeedSMCFlash *fl = opaque;
499fcdf2c59SCédric Le Goater     AspeedSMCState *s = fl->controller;
500924ed163SCédric Le Goater     uint64_t ret = 0;
501924ed163SCédric Le Goater     int i;
502924ed163SCédric Le Goater 
503fcdf2c59SCédric Le Goater     switch (aspeed_smc_flash_mode(fl)) {
504fcdf2c59SCédric Le Goater     case CTRL_USERMODE:
505924ed163SCédric Le Goater         for (i = 0; i < size; i++) {
50675dbf30bSCédric Le Goater             ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
507924ed163SCédric Le Goater         }
508fcdf2c59SCédric Le Goater         break;
509fcdf2c59SCédric Le Goater     case CTRL_READMODE:
510fcdf2c59SCédric Le Goater     case CTRL_FREADMODE:
511fcdf2c59SCédric Le Goater         aspeed_smc_flash_select(fl);
51296c4be95SCédric Le Goater         aspeed_smc_flash_setup(fl, addr);
513ac2810deSCédric Le Goater 
514fcdf2c59SCédric Le Goater         for (i = 0; i < size; i++) {
51575dbf30bSCédric Le Goater             ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
516fcdf2c59SCédric Le Goater         }
517fcdf2c59SCédric Le Goater 
518fcdf2c59SCédric Le Goater         aspeed_smc_flash_unselect(fl);
519fcdf2c59SCédric Le Goater         break;
520fcdf2c59SCédric Le Goater     default:
52132c54bd0SCédric Le Goater         aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
522924ed163SCédric Le Goater     }
523924ed163SCédric Le Goater 
52410f915e4SCédric Le Goater     trace_aspeed_smc_flash_read(fl->cs, addr, size, ret,
525bd6ce9a6SCédric Le Goater                                 aspeed_smc_flash_mode(fl));
526924ed163SCédric Le Goater     return ret;
527924ed163SCédric Le Goater }
528924ed163SCédric Le Goater 
529f95c4bffSCédric Le Goater /*
530f95c4bffSCédric Le Goater  * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
531f95c4bffSCédric Le Goater  * common include header.
532f95c4bffSCédric Le Goater  */
533f95c4bffSCédric Le Goater typedef enum {
534f95c4bffSCédric Le Goater     READ = 0x3,         READ_4 = 0x13,
535f95c4bffSCédric Le Goater     FAST_READ = 0xb,    FAST_READ_4 = 0x0c,
536f95c4bffSCédric Le Goater     DOR = 0x3b,         DOR_4 = 0x3c,
537f95c4bffSCédric Le Goater     QOR = 0x6b,         QOR_4 = 0x6c,
538f95c4bffSCédric Le Goater     DIOR = 0xbb,        DIOR_4 = 0xbc,
539f95c4bffSCédric Le Goater     QIOR = 0xeb,        QIOR_4 = 0xec,
540f95c4bffSCédric Le Goater 
541f95c4bffSCédric Le Goater     PP = 0x2,           PP_4 = 0x12,
542f95c4bffSCédric Le Goater     DPP = 0xa2,
543f95c4bffSCédric Le Goater     QPP = 0x32,         QPP_4 = 0x34,
544f95c4bffSCédric Le Goater } FlashCMD;
545f95c4bffSCédric Le Goater 
aspeed_smc_num_dummies(uint8_t command)546f95c4bffSCédric Le Goater static int aspeed_smc_num_dummies(uint8_t command)
547f95c4bffSCédric Le Goater {
548f95c4bffSCédric Le Goater     switch (command) { /* check for dummies */
549f95c4bffSCédric Le Goater     case READ: /* no dummy bytes/cycles */
550f95c4bffSCédric Le Goater     case PP:
551f95c4bffSCédric Le Goater     case DPP:
552f95c4bffSCédric Le Goater     case QPP:
553f95c4bffSCédric Le Goater     case READ_4:
554f95c4bffSCédric Le Goater     case PP_4:
555f95c4bffSCédric Le Goater     case QPP_4:
556f95c4bffSCédric Le Goater         return 0;
557f95c4bffSCédric Le Goater     case FAST_READ:
558f95c4bffSCédric Le Goater     case DOR:
559f95c4bffSCédric Le Goater     case QOR:
5607faf6f17SGuenter Roeck     case FAST_READ_4:
561f95c4bffSCédric Le Goater     case DOR_4:
562f95c4bffSCédric Le Goater     case QOR_4:
563f95c4bffSCédric Le Goater         return 1;
564f95c4bffSCédric Le Goater     case DIOR:
565f95c4bffSCédric Le Goater     case DIOR_4:
566f95c4bffSCédric Le Goater         return 2;
567f95c4bffSCédric Le Goater     case QIOR:
568f95c4bffSCédric Le Goater     case QIOR_4:
569f95c4bffSCédric Le Goater         return 4;
570f95c4bffSCédric Le Goater     default:
571f95c4bffSCédric Le Goater         return -1;
572f95c4bffSCédric Le Goater     }
573f95c4bffSCédric Le Goater }
574f95c4bffSCédric Le Goater 
aspeed_smc_do_snoop(AspeedSMCFlash * fl,uint64_t data,unsigned size)575f95c4bffSCédric Le Goater static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl,  uint64_t data,
576f95c4bffSCédric Le Goater                                 unsigned size)
577f95c4bffSCédric Le Goater {
578f95c4bffSCédric Le Goater     AspeedSMCState *s = fl->controller;
579a779e37cSCédric Le Goater     uint8_t addr_width = aspeed_smc_flash_addr_width(fl);
580f95c4bffSCédric Le Goater 
58110f915e4SCédric Le Goater     trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
582bd6ce9a6SCédric Le Goater                               (uint8_t) data & 0xff);
583bd6ce9a6SCédric Le Goater 
584f95c4bffSCédric Le Goater     if (s->snoop_index == SNOOP_OFF) {
585f95c4bffSCédric Le Goater         return false; /* Do nothing */
586f95c4bffSCédric Le Goater 
587f95c4bffSCédric Le Goater     } else if (s->snoop_index == SNOOP_START) {
588f95c4bffSCédric Le Goater         uint8_t cmd = data & 0xff;
589f95c4bffSCédric Le Goater         int ndummies = aspeed_smc_num_dummies(cmd);
590f95c4bffSCédric Le Goater 
591f95c4bffSCédric Le Goater         /*
592f95c4bffSCédric Le Goater          * No dummy cycles are expected with the current command. Turn
593f95c4bffSCédric Le Goater          * off snooping and let the transfer proceed normally.
594f95c4bffSCédric Le Goater          */
595f95c4bffSCédric Le Goater         if (ndummies <= 0) {
596f95c4bffSCédric Le Goater             s->snoop_index = SNOOP_OFF;
597f95c4bffSCédric Le Goater             return false;
598f95c4bffSCédric Le Goater         }
599f95c4bffSCédric Le Goater 
600f95c4bffSCédric Le Goater         s->snoop_dummies = ndummies * 8;
601f95c4bffSCédric Le Goater 
602f95c4bffSCédric Le Goater     } else if (s->snoop_index >= addr_width + 1) {
603f95c4bffSCédric Le Goater 
604f95c4bffSCédric Le Goater         /* The SPI transfer has reached the dummy cycles sequence */
605f95c4bffSCédric Le Goater         for (; s->snoop_dummies; s->snoop_dummies--) {
606f95c4bffSCédric Le Goater             ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
607f95c4bffSCédric Le Goater         }
608f95c4bffSCédric Le Goater 
609f95c4bffSCédric Le Goater         /* If no more dummy cycles are expected, turn off snooping */
610f95c4bffSCédric Le Goater         if (!s->snoop_dummies) {
611f95c4bffSCédric Le Goater             s->snoop_index = SNOOP_OFF;
612f95c4bffSCédric Le Goater         } else {
613f95c4bffSCédric Le Goater             s->snoop_index += size;
614f95c4bffSCédric Le Goater         }
615f95c4bffSCédric Le Goater 
616f95c4bffSCédric Le Goater         /*
617f95c4bffSCédric Le Goater          * Dummy cycles have been faked already. Ignore the current
618f95c4bffSCédric Le Goater          * SPI transfer
619f95c4bffSCédric Le Goater          */
620f95c4bffSCédric Le Goater         return true;
621f95c4bffSCédric Le Goater     }
622f95c4bffSCédric Le Goater 
623f95c4bffSCédric Le Goater     s->snoop_index += size;
624f95c4bffSCédric Le Goater     return false;
625f95c4bffSCédric Le Goater }
626f95c4bffSCédric Le Goater 
aspeed_smc_flash_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)627924ed163SCédric Le Goater static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
628924ed163SCédric Le Goater                                    unsigned size)
629924ed163SCédric Le Goater {
630924ed163SCédric Le Goater     AspeedSMCFlash *fl = opaque;
631fcdf2c59SCédric Le Goater     AspeedSMCState *s = fl->controller;
632924ed163SCédric Le Goater     int i;
633924ed163SCédric Le Goater 
63410f915e4SCédric Le Goater     trace_aspeed_smc_flash_write(fl->cs, addr, size, data,
635bd6ce9a6SCédric Le Goater                                  aspeed_smc_flash_mode(fl));
636bd6ce9a6SCédric Le Goater 
637f248a9dbSCédric Le Goater     if (!aspeed_smc_is_writable(fl)) {
63832c54bd0SCédric Le Goater         aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr);
639924ed163SCédric Le Goater         return;
640924ed163SCédric Le Goater     }
641924ed163SCédric Le Goater 
642fcdf2c59SCédric Le Goater     switch (aspeed_smc_flash_mode(fl)) {
643fcdf2c59SCédric Le Goater     case CTRL_USERMODE:
644f95c4bffSCédric Le Goater         if (aspeed_smc_do_snoop(fl, data, size)) {
645f95c4bffSCédric Le Goater             break;
646f95c4bffSCédric Le Goater         }
647f95c4bffSCédric Le Goater 
648fcdf2c59SCédric Le Goater         for (i = 0; i < size; i++) {
649fcdf2c59SCédric Le Goater             ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
650924ed163SCédric Le Goater         }
651fcdf2c59SCédric Le Goater         break;
652fcdf2c59SCédric Le Goater     case CTRL_WRITEMODE:
653fcdf2c59SCédric Le Goater         aspeed_smc_flash_select(fl);
65496c4be95SCédric Le Goater         aspeed_smc_flash_setup(fl, addr);
655924ed163SCédric Le Goater 
656924ed163SCédric Le Goater         for (i = 0; i < size; i++) {
657924ed163SCédric Le Goater             ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
658924ed163SCédric Le Goater         }
659fcdf2c59SCédric Le Goater 
660fcdf2c59SCédric Le Goater         aspeed_smc_flash_unselect(fl);
661fcdf2c59SCédric Le Goater         break;
662fcdf2c59SCédric Le Goater     default:
66332c54bd0SCédric Le Goater         aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
664fcdf2c59SCédric Le Goater     }
665924ed163SCédric Le Goater }
666924ed163SCédric Le Goater 
667924ed163SCédric Le Goater static const MemoryRegionOps aspeed_smc_flash_ops = {
668924ed163SCédric Le Goater     .read = aspeed_smc_flash_read,
669924ed163SCédric Le Goater     .write = aspeed_smc_flash_write,
670924ed163SCédric Le Goater     .endianness = DEVICE_LITTLE_ENDIAN,
671924ed163SCédric Le Goater     .valid = {
672924ed163SCédric Le Goater         .min_access_size = 1,
673*47cdaa46SJoe Komlodi         .max_access_size = 8,
674924ed163SCédric Le Goater     },
6757c1c69bcSCédric Le Goater };
6767c1c69bcSCédric Le Goater 
aspeed_smc_flash_update_ctrl(AspeedSMCFlash * fl,uint32_t value)677e7e741caSCédric Le Goater static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
6787c1c69bcSCédric Le Goater {
679f95c4bffSCédric Le Goater     AspeedSMCState *s = fl->controller;
68005d501a1SJamin Lin     bool unselect = false;
68105d501a1SJamin Lin     uint32_t old_mode;
68205d501a1SJamin Lin     uint32_t new_mode;
683f95c4bffSCédric Le Goater 
68405d501a1SJamin Lin     old_mode = s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK;
68505d501a1SJamin Lin     new_mode = value & CTRL_CMD_MODE_MASK;
68605d501a1SJamin Lin 
68705d501a1SJamin Lin     if (old_mode == CTRL_USERMODE) {
68805d501a1SJamin Lin         if (new_mode != CTRL_USERMODE) {
68905d501a1SJamin Lin             unselect = true;
69005d501a1SJamin Lin         }
6917c1c69bcSCédric Le Goater 
692e7e741caSCédric Le Goater         /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
69310f915e4SCédric Le Goater         if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) &&
694e7e741caSCédric Le Goater             value & CTRL_CE_STOP_ACTIVE) {
695e7e741caSCédric Le Goater             unselect = true;
696e7e741caSCédric Le Goater         }
69705d501a1SJamin Lin     } else {
69805d501a1SJamin Lin         if (new_mode != CTRL_USERMODE) {
69905d501a1SJamin Lin             unselect = true;
70005d501a1SJamin Lin         }
70105d501a1SJamin Lin     }
702e7e741caSCédric Le Goater 
70310f915e4SCédric Le Goater     s->regs[s->r_ctrl0 + fl->cs] = value;
704e7e741caSCédric Le Goater 
70505d501a1SJamin Lin     if (unselect != s->unselect) {
706e7e741caSCédric Le Goater         s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
707e7e741caSCédric Le Goater         aspeed_smc_flash_do_select(fl, unselect);
7087c1c69bcSCédric Le Goater     }
70905d501a1SJamin Lin }
7107c1c69bcSCédric Le Goater 
aspeed_smc_reset(DeviceState * d)7117c1c69bcSCédric Le Goater static void aspeed_smc_reset(DeviceState *d)
7127c1c69bcSCédric Le Goater {
7137c1c69bcSCédric Le Goater     AspeedSMCState *s = ASPEED_SMC(d);
71430b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
7157c1c69bcSCédric Le Goater     int i;
7167c1c69bcSCédric Le Goater 
71771255c48SCédric Le Goater     if (asc->resets) {
71871255c48SCédric Le Goater         memcpy(s->regs, asc->resets, sizeof s->regs);
71971255c48SCédric Le Goater     } else {
7207c1c69bcSCédric Le Goater         memset(s->regs, 0, sizeof s->regs);
72171255c48SCédric Le Goater     }
7227c1c69bcSCédric Le Goater 
72327a2c66cSCédric Le Goater     for (i = 0; i < asc->cs_num_max; i++) {
72427a2c66cSCédric Le Goater         DeviceState *dev = ssi_get_cs(s->spi, i);
72527a2c66cSCédric Le Goater         if (dev) {
726a7538ca0SCédric Le Goater             Object *o = OBJECT(dev);
727a7538ca0SCédric Le Goater 
728a7538ca0SCédric Le Goater             if (!object_dynamic_cast(o, TYPE_M25P80)) {
729a7538ca0SCédric Le Goater                 warn_report("Aspeed SMC %s.%d : Invalid %s device type",
730a7538ca0SCédric Le Goater                             BUS(s->spi)->name, i, object_get_typename(o));
731a7538ca0SCédric Le Goater                 continue;
732a7538ca0SCédric Le Goater             }
733a7538ca0SCédric Le Goater 
73427a2c66cSCédric Le Goater             qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
73527a2c66cSCédric Le Goater             qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
73627a2c66cSCédric Le Goater         }
73727a2c66cSCédric Le Goater     }
73827a2c66cSCédric Le Goater 
7395ade579bSPhilippe Mathieu-Daudé     /* Unselect all peripherals */
740ae945a00SCédric Le Goater     for (i = 0; i < asc->cs_num_max; ++i) {
7417c1c69bcSCédric Le Goater         s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
7421d247bd0SCédric Le Goater         qemu_set_irq(s->cs_lines[i], true);
7437c1c69bcSCédric Le Goater     }
7447c1c69bcSCédric Le Goater 
74505d501a1SJamin Lin     s->unselect = true;
74605d501a1SJamin Lin 
747673b1f86SCédric Le Goater     /* setup the default segment register values and regions for all */
748ae945a00SCédric Le Goater     for (i = 0; i < asc->cs_num_max; ++i) {
749673b1f86SCédric Le Goater         aspeed_smc_flash_set_segment_region(s, i,
75030b6852cSCédric Le Goater                     asc->segment_to_reg(s, &asc->segments[i]));
751a03cb1daSCédric Le Goater     }
7520707b34dSCédric Le Goater 
753f95c4bffSCédric Le Goater     s->snoop_index = SNOOP_OFF;
754f95c4bffSCédric Le Goater     s->snoop_dummies = 0;
7557c1c69bcSCédric Le Goater }
7567c1c69bcSCédric Le Goater 
aspeed_smc_read(void * opaque,hwaddr addr,unsigned int size)7577c1c69bcSCédric Le Goater static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
7587c1c69bcSCédric Le Goater {
7597c1c69bcSCédric Le Goater     AspeedSMCState *s = ASPEED_SMC(opaque);
76030b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque);
7617c1c69bcSCédric Le Goater 
7627c1c69bcSCédric Le Goater     addr >>= 2;
7637c1c69bcSCédric Le Goater 
76497c2ed5dSCédric Le Goater     if (addr == s->r_conf ||
765f286f04cSCédric Le Goater         (addr >= s->r_timings &&
76630b6852cSCédric Le Goater          addr < s->r_timings + asc->nregs_timings) ||
76797c2ed5dSCédric Le Goater         addr == s->r_ce_ctrl ||
768af453a5eSCédric Le Goater         addr == R_CE_CMD_CTRL ||
7692e1f0502SCédric Le Goater         addr == R_INTR_CTRL ||
7709149af2aSCédric Le Goater         addr == R_DUMMY_DATA ||
77130b6852cSCédric Le Goater         (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) ||
77230b6852cSCédric Le Goater         (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||
77330b6852cSCédric Le Goater         (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||
77430b6852cSCédric Le Goater         (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||
7756330be8dSJamin Lin         (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&
7766330be8dSJamin Lin          addr == R_DMA_DRAM_ADDR_HIGH) ||
77730b6852cSCédric Le Goater         (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||
77830b6852cSCédric Le Goater         (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||
7795ade579bSPhilippe Mathieu-Daudé         (addr >= R_SEG_ADDR0 &&
780ae945a00SCédric Le Goater          addr < R_SEG_ADDR0 + asc->cs_num_max) ||
781ae945a00SCédric Le Goater         (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) {
782bd6ce9a6SCédric Le Goater 
783e2804a1eSCédric Le Goater         trace_aspeed_smc_read(addr << 2, size, s->regs[addr]);
784bd6ce9a6SCédric Le Goater 
78597c2ed5dSCédric Le Goater         return s->regs[addr];
78697c2ed5dSCédric Le Goater     } else {
7877c1c69bcSCédric Le Goater         qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
7887c1c69bcSCédric Le Goater                       __func__, addr);
789b617ca92SCédric Le Goater         return -1;
7907c1c69bcSCédric Le Goater     }
7917c1c69bcSCédric Le Goater }
7927c1c69bcSCédric Le Goater 
aspeed_smc_hclk_divisor(uint8_t hclk_mask)7930d72c717SCédric Le Goater static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
7940d72c717SCédric Le Goater {
7950d72c717SCédric Le Goater     /* HCLK/1 .. HCLK/16 */
7960d72c717SCédric Le Goater     const uint8_t hclk_divisors[] = {
7970d72c717SCédric Le Goater         15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
7980d72c717SCédric Le Goater     };
7990d72c717SCédric Le Goater     int i;
8000d72c717SCédric Le Goater 
8010d72c717SCédric Le Goater     for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
8020d72c717SCédric Le Goater         if (hclk_mask == hclk_divisors[i]) {
8030d72c717SCédric Le Goater             return i + 1;
8040d72c717SCédric Le Goater         }
8050d72c717SCédric Le Goater     }
8060d72c717SCédric Le Goater 
80713951ccfSCédric Le Goater     g_assert_not_reached();
8080d72c717SCédric Le Goater }
8090d72c717SCédric Le Goater 
8100d72c717SCédric Le Goater /*
8110d72c717SCédric Le Goater  * When doing calibration, the SPI clock rate in the CE0 Control
8120d72c717SCédric Le Goater  * Register and the read delay cycles in the Read Timing Compensation
8130d72c717SCédric Le Goater  * Register are set using bit[11:4] of the DMA Control Register.
8140d72c717SCédric Le Goater  */
aspeed_smc_dma_calibration(AspeedSMCState * s)8150d72c717SCédric Le Goater static void aspeed_smc_dma_calibration(AspeedSMCState *s)
8160d72c717SCédric Le Goater {
8170d72c717SCédric Le Goater     uint8_t delay =
8180d72c717SCédric Le Goater         (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
8190d72c717SCédric Le Goater     uint8_t hclk_mask =
8200d72c717SCédric Le Goater         (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
8210d72c717SCédric Le Goater     uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
8220d72c717SCédric Le Goater     uint32_t hclk_shift = (hclk_div - 1) << 2;
8230d72c717SCédric Le Goater     uint8_t cs;
8240d72c717SCédric Le Goater 
8250d72c717SCédric Le Goater     /*
8260d72c717SCédric Le Goater      * The Read Timing Compensation Register values apply to all CS on
8270d72c717SCédric Le Goater      * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
8280d72c717SCédric Le Goater      */
8290d72c717SCédric Le Goater     if (hclk_div && hclk_div < 6) {
8300d72c717SCédric Le Goater         s->regs[s->r_timings] &= ~(0xf << hclk_shift);
8310d72c717SCédric Le Goater         s->regs[s->r_timings] |= delay << hclk_shift;
8320d72c717SCédric Le Goater     }
8330d72c717SCédric Le Goater 
8340d72c717SCédric Le Goater     /*
8350d72c717SCédric Le Goater      * TODO: compute the CS from the DMA address and the segment
8360d72c717SCédric Le Goater      * registers. This is not really a problem for now because the
8370d72c717SCédric Le Goater      * Timing Register values apply to all CS and software uses CS0 to
8380d72c717SCédric Le Goater      * do calibration.
8390d72c717SCédric Le Goater      */
8400d72c717SCédric Le Goater     cs = 0;
8410d72c717SCédric Le Goater     s->regs[s->r_ctrl0 + cs] &=
8420d72c717SCédric Le Goater         ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
8430d72c717SCédric Le Goater     s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
8440d72c717SCédric Le Goater }
8450d72c717SCédric Le Goater 
846c4e1f0b4SCédric Le Goater /*
8475258c2a6SCédric Le Goater  * Emulate read errors in the DMA Checksum Register for high
8485258c2a6SCédric Le Goater  * frequencies and optimistic settings of the Read Timing Compensation
8495258c2a6SCédric Le Goater  * Register. This will help in tuning the SPI timing calibration
8505258c2a6SCédric Le Goater  * algorithm.
8515258c2a6SCédric Le Goater  */
aspeed_smc_inject_read_failure(AspeedSMCState * s)8525258c2a6SCédric Le Goater static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
8535258c2a6SCédric Le Goater {
8545258c2a6SCédric Le Goater     uint8_t delay =
8555258c2a6SCédric Le Goater         (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
8565258c2a6SCédric Le Goater     uint8_t hclk_mask =
8575258c2a6SCédric Le Goater         (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
8585258c2a6SCédric Le Goater 
8595258c2a6SCédric Le Goater     /*
8605258c2a6SCédric Le Goater      * Typical values of a palmetto-bmc machine.
8615258c2a6SCédric Le Goater      */
8625258c2a6SCédric Le Goater     switch (aspeed_smc_hclk_divisor(hclk_mask)) {
8635258c2a6SCédric Le Goater     case 4 ... 16:
8645258c2a6SCédric Le Goater         return false;
8655258c2a6SCédric Le Goater     case 3: /* at least one HCLK cycle delay */
8665258c2a6SCédric Le Goater         return (delay & 0x7) < 1;
8675258c2a6SCédric Le Goater     case 2: /* at least two HCLK cycle delay */
8685258c2a6SCédric Le Goater         return (delay & 0x7) < 2;
8695258c2a6SCédric Le Goater     case 1: /* (> 100MHz) is above the max freq of the controller */
8705258c2a6SCédric Le Goater         return true;
8715258c2a6SCédric Le Goater     default:
8725258c2a6SCédric Le Goater         g_assert_not_reached();
8735258c2a6SCédric Le Goater     }
8745258c2a6SCédric Le Goater }
8755258c2a6SCédric Le Goater 
aspeed_smc_dma_dram_addr(AspeedSMCState * s)8766330be8dSJamin Lin static uint64_t aspeed_smc_dma_dram_addr(AspeedSMCState *s)
8776330be8dSJamin Lin {
8786330be8dSJamin Lin     return s->regs[R_DMA_DRAM_ADDR] |
8796330be8dSJamin Lin         ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32);
8806330be8dSJamin Lin }
8816330be8dSJamin Lin 
aspeed_smc_dma_len(AspeedSMCState * s)8823a6c0f0eSJamin Lin static uint32_t aspeed_smc_dma_len(AspeedSMCState *s)
8833a6c0f0eSJamin Lin {
8843a6c0f0eSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
8853a6c0f0eSJamin Lin 
8863a6c0f0eSJamin Lin     return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4);
8873a6c0f0eSJamin Lin }
8883a6c0f0eSJamin Lin 
8895258c2a6SCédric Le Goater /*
890c4e1f0b4SCédric Le Goater  * Accumulate the result of the reads to provide a checksum that will
891c4e1f0b4SCédric Le Goater  * be used to validate the read timing settings.
892c4e1f0b4SCédric Le Goater  */
aspeed_smc_dma_checksum(AspeedSMCState * s)893c4e1f0b4SCédric Le Goater static void aspeed_smc_dma_checksum(AspeedSMCState *s)
894c4e1f0b4SCédric Le Goater {
895c4e1f0b4SCédric Le Goater     MemTxResult result;
8963a6c0f0eSJamin Lin     uint32_t dma_len;
897c4e1f0b4SCédric Le Goater     uint32_t data;
898c4e1f0b4SCédric Le Goater 
899c4e1f0b4SCédric Le Goater     if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
90032c54bd0SCédric Le Goater         aspeed_smc_error("invalid direction for DMA checksum");
901c4e1f0b4SCédric Le Goater         return;
902c4e1f0b4SCédric Le Goater     }
903c4e1f0b4SCédric Le Goater 
9040d72c717SCédric Le Goater     if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
9050d72c717SCédric Le Goater         aspeed_smc_dma_calibration(s);
9060d72c717SCédric Le Goater     }
9070d72c717SCédric Le Goater 
9083a6c0f0eSJamin Lin     dma_len = aspeed_smc_dma_len(s);
9093a6c0f0eSJamin Lin 
9103a6c0f0eSJamin Lin     while (dma_len) {
911c4e1f0b4SCédric Le Goater         data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
912c4e1f0b4SCédric Le Goater                                     MEMTXATTRS_UNSPECIFIED, &result);
913c4e1f0b4SCédric Le Goater         if (result != MEMTX_OK) {
91432c54bd0SCédric Le Goater             aspeed_smc_error("Flash read failed @%08x",
91532c54bd0SCédric Le Goater                              s->regs[R_DMA_FLASH_ADDR]);
916c4e1f0b4SCédric Le Goater             return;
917c4e1f0b4SCédric Le Goater         }
918bd6ce9a6SCédric Le Goater         trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
919c4e1f0b4SCédric Le Goater 
920c4e1f0b4SCédric Le Goater         /*
921c4e1f0b4SCédric Le Goater          * When the DMA is on-going, the DMA registers are updated
922c4e1f0b4SCédric Le Goater          * with the current working addresses and length.
923c4e1f0b4SCédric Le Goater          */
924c4e1f0b4SCédric Le Goater         s->regs[R_DMA_CHECKSUM] += data;
925c4e1f0b4SCédric Le Goater         s->regs[R_DMA_FLASH_ADDR] += 4;
9263a6c0f0eSJamin Lin         dma_len -= 4;
9273a6c0f0eSJamin Lin         s->regs[R_DMA_LEN] = dma_len;
928c4e1f0b4SCédric Le Goater     }
9295258c2a6SCédric Le Goater 
9305258c2a6SCédric Le Goater     if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
9315258c2a6SCédric Le Goater         s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
9325258c2a6SCédric Le Goater     }
9335258c2a6SCédric Le Goater 
934c4e1f0b4SCédric Le Goater }
935c4e1f0b4SCédric Le Goater 
aspeed_smc_dma_rw(AspeedSMCState * s)936c4e1f0b4SCédric Le Goater static void aspeed_smc_dma_rw(AspeedSMCState *s)
937c4e1f0b4SCédric Le Goater {
9386330be8dSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
9396330be8dSJamin Lin     uint64_t dma_dram_offset;
9406330be8dSJamin Lin     uint64_t dma_dram_addr;
941c4e1f0b4SCédric Le Goater     MemTxResult result;
9423a6c0f0eSJamin Lin     uint32_t dma_len;
943c4e1f0b4SCédric Le Goater     uint32_t data;
944c4e1f0b4SCédric Le Goater 
9453a6c0f0eSJamin Lin     dma_len = aspeed_smc_dma_len(s);
9466330be8dSJamin Lin     dma_dram_addr = aspeed_smc_dma_dram_addr(s);
9476330be8dSJamin Lin 
9486330be8dSJamin Lin     if (aspeed_smc_has_dma64(asc)) {
9496330be8dSJamin Lin         dma_dram_offset = dma_dram_addr - s->dram_base;
9506330be8dSJamin Lin     } else {
9516330be8dSJamin Lin         dma_dram_offset = dma_dram_addr;
9526330be8dSJamin Lin     }
9533a6c0f0eSJamin Lin 
9544dabf395SCédric Le Goater     trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
9554dabf395SCédric Le Goater                             "write" : "read",
9564dabf395SCédric Le Goater                             s->regs[R_DMA_FLASH_ADDR],
9576330be8dSJamin Lin                             dma_dram_offset,
9583a6c0f0eSJamin Lin                             dma_len);
9593a6c0f0eSJamin Lin     while (dma_len) {
960c4e1f0b4SCédric Le Goater         if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
9616330be8dSJamin Lin             data = address_space_ldl_le(&s->dram_as, dma_dram_offset,
962c4e1f0b4SCédric Le Goater                                         MEMTXATTRS_UNSPECIFIED, &result);
963c4e1f0b4SCédric Le Goater             if (result != MEMTX_OK) {
9646330be8dSJamin Lin                 aspeed_smc_error("DRAM read failed @%" PRIx64,
9656330be8dSJamin Lin                                  dma_dram_offset);
966c4e1f0b4SCédric Le Goater                 return;
967c4e1f0b4SCédric Le Goater             }
968c4e1f0b4SCédric Le Goater 
969c4e1f0b4SCédric Le Goater             address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
970c4e1f0b4SCédric Le Goater                                  data, MEMTXATTRS_UNSPECIFIED, &result);
971c4e1f0b4SCédric Le Goater             if (result != MEMTX_OK) {
97232c54bd0SCédric Le Goater                 aspeed_smc_error("Flash write failed @%08x",
97332c54bd0SCédric Le Goater                                  s->regs[R_DMA_FLASH_ADDR]);
974c4e1f0b4SCédric Le Goater                 return;
975c4e1f0b4SCédric Le Goater             }
976c4e1f0b4SCédric Le Goater         } else {
977c4e1f0b4SCédric Le Goater             data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
978c4e1f0b4SCédric Le Goater                                         MEMTXATTRS_UNSPECIFIED, &result);
979c4e1f0b4SCédric Le Goater             if (result != MEMTX_OK) {
98032c54bd0SCédric Le Goater                 aspeed_smc_error("Flash read failed @%08x",
98132c54bd0SCédric Le Goater                                  s->regs[R_DMA_FLASH_ADDR]);
982c4e1f0b4SCédric Le Goater                 return;
983c4e1f0b4SCédric Le Goater             }
984c4e1f0b4SCédric Le Goater 
9856330be8dSJamin Lin             address_space_stl_le(&s->dram_as, dma_dram_offset,
986c4e1f0b4SCédric Le Goater                                  data, MEMTXATTRS_UNSPECIFIED, &result);
987c4e1f0b4SCédric Le Goater             if (result != MEMTX_OK) {
9886330be8dSJamin Lin                 aspeed_smc_error("DRAM write failed @%" PRIx64,
9896330be8dSJamin Lin                                  dma_dram_offset);
990c4e1f0b4SCédric Le Goater                 return;
991c4e1f0b4SCédric Le Goater             }
992c4e1f0b4SCédric Le Goater         }
993c4e1f0b4SCédric Le Goater 
994c4e1f0b4SCédric Le Goater         /*
995c4e1f0b4SCédric Le Goater          * When the DMA is on-going, the DMA registers are updated
996c4e1f0b4SCédric Le Goater          * with the current working addresses and length.
997c4e1f0b4SCédric Le Goater          */
9986330be8dSJamin Lin         dma_dram_offset += 4;
9996330be8dSJamin Lin         dma_dram_addr += 4;
10006330be8dSJamin Lin 
10016330be8dSJamin Lin         s->regs[R_DMA_DRAM_ADDR_HIGH] = dma_dram_addr >> 32;
10026330be8dSJamin Lin         s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff;
1003c4e1f0b4SCédric Le Goater         s->regs[R_DMA_FLASH_ADDR] += 4;
10043a6c0f0eSJamin Lin         dma_len -= 4;
10053a6c0f0eSJamin Lin         s->regs[R_DMA_LEN] = dma_len;
1006ae275f71SChristian Svensson         s->regs[R_DMA_CHECKSUM] += data;
1007c4e1f0b4SCédric Le Goater     }
1008c4e1f0b4SCédric Le Goater }
1009c4e1f0b4SCédric Le Goater 
aspeed_smc_dma_stop(AspeedSMCState * s)1010c4e1f0b4SCédric Le Goater static void aspeed_smc_dma_stop(AspeedSMCState *s)
1011c4e1f0b4SCédric Le Goater {
1012c4e1f0b4SCédric Le Goater     /*
1013c4e1f0b4SCédric Le Goater      * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
1014c4e1f0b4SCédric Le Goater      * engine is idle
1015c4e1f0b4SCédric Le Goater      */
1016c4e1f0b4SCédric Le Goater     s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
1017c4e1f0b4SCédric Le Goater     s->regs[R_DMA_CHECKSUM] = 0;
1018c4e1f0b4SCédric Le Goater 
1019c4e1f0b4SCédric Le Goater     /*
1020c4e1f0b4SCédric Le Goater      * Lower the DMA irq in any case. The IRQ control register could
1021c4e1f0b4SCédric Le Goater      * have been cleared before disabling the DMA.
1022c4e1f0b4SCédric Le Goater      */
1023c4e1f0b4SCédric Le Goater     qemu_irq_lower(s->irq);
1024c4e1f0b4SCédric Le Goater }
1025c4e1f0b4SCédric Le Goater 
1026c4e1f0b4SCédric Le Goater /*
1027c4e1f0b4SCédric Le Goater  * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
1028c4e1f0b4SCédric Le Goater  * can start even if the result of the previous was not collected.
1029c4e1f0b4SCédric Le Goater  */
aspeed_smc_dma_in_progress(AspeedSMCState * s)1030c4e1f0b4SCédric Le Goater static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
1031c4e1f0b4SCédric Le Goater {
1032c4e1f0b4SCédric Le Goater     return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
1033c4e1f0b4SCédric Le Goater         !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
1034c4e1f0b4SCédric Le Goater }
1035c4e1f0b4SCédric Le Goater 
aspeed_smc_dma_done(AspeedSMCState * s)1036c4e1f0b4SCédric Le Goater static void aspeed_smc_dma_done(AspeedSMCState *s)
1037c4e1f0b4SCédric Le Goater {
1038c4e1f0b4SCédric Le Goater     s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
1039c4e1f0b4SCédric Le Goater     if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
1040c4e1f0b4SCédric Le Goater         qemu_irq_raise(s->irq);
1041c4e1f0b4SCédric Le Goater     }
1042c4e1f0b4SCédric Le Goater }
1043c4e1f0b4SCédric Le Goater 
aspeed_smc_dma_ctrl(AspeedSMCState * s,uint32_t dma_ctrl)10441769a70eSCédric Le Goater static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
1045c4e1f0b4SCédric Le Goater {
1046c4e1f0b4SCédric Le Goater     if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
1047c4e1f0b4SCédric Le Goater         s->regs[R_DMA_CTRL] = dma_ctrl;
1048c4e1f0b4SCédric Le Goater 
1049c4e1f0b4SCédric Le Goater         aspeed_smc_dma_stop(s);
1050c4e1f0b4SCédric Le Goater         return;
1051c4e1f0b4SCédric Le Goater     }
1052c4e1f0b4SCédric Le Goater 
1053c4e1f0b4SCédric Le Goater     if (aspeed_smc_dma_in_progress(s)) {
105432c54bd0SCédric Le Goater         aspeed_smc_error("DMA in progress !");
1055c4e1f0b4SCédric Le Goater         return;
1056c4e1f0b4SCédric Le Goater     }
1057c4e1f0b4SCédric Le Goater 
1058c4e1f0b4SCédric Le Goater     s->regs[R_DMA_CTRL] = dma_ctrl;
1059c4e1f0b4SCédric Le Goater 
1060c4e1f0b4SCédric Le Goater     if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
1061c4e1f0b4SCédric Le Goater         aspeed_smc_dma_checksum(s);
1062c4e1f0b4SCédric Le Goater     } else {
1063c4e1f0b4SCédric Le Goater         aspeed_smc_dma_rw(s);
1064c4e1f0b4SCédric Le Goater     }
1065c4e1f0b4SCédric Le Goater 
1066c4e1f0b4SCédric Le Goater     aspeed_smc_dma_done(s);
1067c4e1f0b4SCédric Le Goater }
1068c4e1f0b4SCédric Le Goater 
aspeed_smc_dma_granted(AspeedSMCState * s)10691769a70eSCédric Le Goater static inline bool aspeed_smc_dma_granted(AspeedSMCState *s)
10701769a70eSCédric Le Goater {
107130b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
107230b6852cSCédric Le Goater 
107330b6852cSCédric Le Goater     if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) {
10741769a70eSCédric Le Goater         return true;
10751769a70eSCédric Le Goater     }
10761769a70eSCédric Le Goater 
10771769a70eSCédric Le Goater     if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {
107832c54bd0SCédric Le Goater         aspeed_smc_error("DMA not granted");
10791769a70eSCédric Le Goater         return false;
10801769a70eSCédric Le Goater     }
10811769a70eSCédric Le Goater 
10821769a70eSCédric Le Goater     return true;
10831769a70eSCédric Le Goater }
10841769a70eSCédric Le Goater 
aspeed_2600_smc_dma_ctrl(AspeedSMCState * s,uint32_t dma_ctrl)10851769a70eSCédric Le Goater static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
10861769a70eSCédric Le Goater {
10871769a70eSCédric Le Goater     /* Preserve DMA bits  */
10881769a70eSCédric Le Goater     dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
10891769a70eSCédric Le Goater 
10901769a70eSCédric Le Goater     if (dma_ctrl == 0xAEED0000) {
10911769a70eSCédric Le Goater         /* automatically grant request */
10921769a70eSCédric Le Goater         s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
10931769a70eSCédric Le Goater         return;
10941769a70eSCédric Le Goater     }
10951769a70eSCédric Le Goater 
10961769a70eSCédric Le Goater     /* clear request */
10971769a70eSCédric Le Goater     if (dma_ctrl == 0xDEEA0000) {
10981769a70eSCédric Le Goater         s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
10991769a70eSCédric Le Goater         return;
11001769a70eSCédric Le Goater     }
11011769a70eSCédric Le Goater 
11021769a70eSCédric Le Goater     if (!aspeed_smc_dma_granted(s)) {
110332c54bd0SCédric Le Goater         aspeed_smc_error("DMA not granted");
11041769a70eSCédric Le Goater         return;
11051769a70eSCédric Le Goater     }
11061769a70eSCédric Le Goater 
11071769a70eSCédric Le Goater     aspeed_smc_dma_ctrl(s, dma_ctrl);
11081769a70eSCédric Le Goater     s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
11091769a70eSCédric Le Goater }
11101769a70eSCédric Le Goater 
aspeed_smc_write(void * opaque,hwaddr addr,uint64_t data,unsigned int size)11117c1c69bcSCédric Le Goater static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
11127c1c69bcSCédric Le Goater                              unsigned int size)
11137c1c69bcSCédric Le Goater {
11147c1c69bcSCédric Le Goater     AspeedSMCState *s = ASPEED_SMC(opaque);
111530b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
11167c1c69bcSCédric Le Goater     uint32_t value = data;
11177c1c69bcSCédric Le Goater 
1118bd6ce9a6SCédric Le Goater     trace_aspeed_smc_write(addr, size, data);
1119bd6ce9a6SCédric Le Goater 
1120e2804a1eSCédric Le Goater     addr >>= 2;
1121e2804a1eSCédric Le Goater 
112297c2ed5dSCédric Le Goater     if (addr == s->r_conf ||
1123f286f04cSCédric Le Goater         (addr >= s->r_timings &&
112430b6852cSCédric Le Goater          addr < s->r_timings + asc->nregs_timings) ||
112597c2ed5dSCédric Le Goater         addr == s->r_ce_ctrl) {
112697c2ed5dSCédric Le Goater         s->regs[addr] = value;
1127ae945a00SCédric Le Goater     } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) {
1128f248a9dbSCédric Le Goater         int cs = addr - s->r_ctrl0;
1129e7e741caSCédric Le Goater         aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
1130a03cb1daSCédric Le Goater     } else if (addr >= R_SEG_ADDR0 &&
1131ae945a00SCédric Le Goater                addr < R_SEG_ADDR0 + asc->cs_num_max) {
1132a03cb1daSCédric Le Goater         int cs = addr - R_SEG_ADDR0;
1133a03cb1daSCédric Le Goater 
1134a03cb1daSCédric Le Goater         if (value != s->regs[R_SEG_ADDR0 + cs]) {
1135a03cb1daSCédric Le Goater             aspeed_smc_flash_set_segment(s, cs, value);
1136a03cb1daSCédric Le Goater         }
1137af453a5eSCédric Le Goater     } else if (addr == R_CE_CMD_CTRL) {
1138af453a5eSCédric Le Goater         s->regs[addr] = value & 0xff;
11399149af2aSCédric Le Goater     } else if (addr == R_DUMMY_DATA) {
11409149af2aSCédric Le Goater         s->regs[addr] = value & 0xff;
114130b6852cSCédric Le Goater     } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) {
114245a904afSCédric Le Goater         s->regs[addr] = value & FMC_WDT2_CTRL_EN;
1143c4e1f0b4SCédric Le Goater     } else if (addr == R_INTR_CTRL) {
1144c4e1f0b4SCédric Le Goater         s->regs[addr] = value;
114530b6852cSCédric Le Goater     } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) {
114630b6852cSCédric Le Goater         asc->dma_ctrl(s, value);
114730b6852cSCédric Le Goater     } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR &&
11481769a70eSCédric Le Goater                aspeed_smc_dma_granted(s)) {
114930b6852cSCédric Le Goater         s->regs[addr] = DMA_DRAM_ADDR(asc, value);
115030b6852cSCédric Le Goater     } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR &&
11511769a70eSCédric Le Goater                aspeed_smc_dma_granted(s)) {
115230b6852cSCédric Le Goater         s->regs[addr] = DMA_FLASH_ADDR(asc, value);
115330b6852cSCédric Le Goater     } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&
11541769a70eSCédric Le Goater                aspeed_smc_dma_granted(s)) {
1155c4e1f0b4SCédric Le Goater         s->regs[addr] = DMA_LENGTH(value);
11566330be8dSJamin Lin     } else if (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&
11576330be8dSJamin Lin                addr == R_DMA_DRAM_ADDR_HIGH) {
11586330be8dSJamin Lin         s->regs[addr] = DMA_DRAM_ADDR_HIGH(value);
115997c2ed5dSCédric Le Goater     } else {
11607c1c69bcSCédric Le Goater         qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
11617c1c69bcSCédric Le Goater                       __func__, addr);
11627c1c69bcSCédric Le Goater         return;
11637c1c69bcSCédric Le Goater     }
11647c1c69bcSCédric Le Goater }
11657c1c69bcSCédric Le Goater 
11667c1c69bcSCédric Le Goater static const MemoryRegionOps aspeed_smc_ops = {
11677c1c69bcSCédric Le Goater     .read = aspeed_smc_read,
11687c1c69bcSCédric Le Goater     .write = aspeed_smc_write,
11697c1c69bcSCédric Le Goater     .endianness = DEVICE_LITTLE_ENDIAN,
11707c1c69bcSCédric Le Goater };
11717c1c69bcSCédric Le Goater 
aspeed_smc_instance_init(Object * obj)1172f75b5331SCédric Le Goater static void aspeed_smc_instance_init(Object *obj)
1173f75b5331SCédric Le Goater {
1174f75b5331SCédric Le Goater     AspeedSMCState *s = ASPEED_SMC(obj);
1175f75b5331SCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1176f75b5331SCédric Le Goater     int i;
1177f75b5331SCédric Le Goater 
1178ae945a00SCédric Le Goater     for (i = 0; i < asc->cs_num_max; i++) {
1179f75b5331SCédric Le Goater         object_initialize_child(obj, "flash[*]", &s->flashes[i],
1180f75b5331SCédric Le Goater                                 TYPE_ASPEED_SMC_FLASH);
1181f75b5331SCédric Le Goater     }
1182f75b5331SCédric Le Goater }
1183f75b5331SCédric Le Goater 
1184c4e1f0b4SCédric Le Goater /*
1185c4e1f0b4SCédric Le Goater  * Initialize the custom address spaces for DMAs
1186c4e1f0b4SCédric Le Goater  */
aspeed_smc_dma_setup(AspeedSMCState * s,Error ** errp)1187c4e1f0b4SCédric Le Goater static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
1188c4e1f0b4SCédric Le Goater {
1189c4e1f0b4SCédric Le Goater     if (!s->dram_mr) {
1190c4e1f0b4SCédric Le Goater         error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
1191c4e1f0b4SCédric Le Goater         return;
1192c4e1f0b4SCédric Le Goater     }
1193c4e1f0b4SCédric Le Goater 
1194d0180a3aSCédric Le Goater     address_space_init(&s->flash_as, &s->mmio_flash,
1195d0180a3aSCédric Le Goater                        TYPE_ASPEED_SMC ".dma-flash");
1196d0180a3aSCédric Le Goater     address_space_init(&s->dram_as, s->dram_mr,
1197d0180a3aSCédric Le Goater                        TYPE_ASPEED_SMC ".dma-dram");
1198c4e1f0b4SCédric Le Goater }
1199c4e1f0b4SCédric Le Goater 
aspeed_smc_realize(DeviceState * dev,Error ** errp)12007c1c69bcSCédric Le Goater static void aspeed_smc_realize(DeviceState *dev, Error **errp)
12017c1c69bcSCédric Le Goater {
12027c1c69bcSCédric Le Goater     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
12037c1c69bcSCédric Le Goater     AspeedSMCState *s = ASPEED_SMC(dev);
120430b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
12057c1c69bcSCédric Le Goater     int i;
1206924ed163SCédric Le Goater     hwaddr offset = 0;
12077c1c69bcSCédric Le Goater 
12087c1c69bcSCédric Le Goater     /* keep a copy under AspeedSMCState to speed up accesses */
120930b6852cSCédric Le Goater     s->r_conf = asc->r_conf;
121030b6852cSCédric Le Goater     s->r_ce_ctrl = asc->r_ce_ctrl;
121130b6852cSCédric Le Goater     s->r_ctrl0 = asc->r_ctrl0;
121230b6852cSCédric Le Goater     s->r_timings = asc->r_timings;
121330b6852cSCédric Le Goater     s->conf_enable_w0 = asc->conf_enable_w0;
12147c1c69bcSCédric Le Goater 
1215c4e1f0b4SCédric Le Goater     /* DMA irq. Keep it first for the initialization in the SoC */
1216c4e1f0b4SCédric Le Goater     sysbus_init_irq(sbd, &s->irq);
1217c4e1f0b4SCédric Le Goater 
12189bbdfe05SCédric Le Goater     s->spi = ssi_create_bus(dev, NULL);
12197c1c69bcSCédric Le Goater 
12205ade579bSPhilippe Mathieu-Daudé     /* Setup cs_lines for peripherals */
1221ae945a00SCédric Le Goater     s->cs_lines = g_new0(qemu_irq, asc->cs_num_max);
1222b22a2d40SCédric Le Goater     qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max);
12237c1c69bcSCédric Le Goater 
12242da95fd8SCédric Le Goater     /* The memory region for the controller registers */
12257c1c69bcSCédric Le Goater     memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
122630b6852cSCédric Le Goater                           TYPE_ASPEED_SMC, asc->nregs * 4);
12277c1c69bcSCédric Le Goater     sysbus_init_mmio(sbd, &s->mmio);
1228924ed163SCédric Le Goater 
1229924ed163SCédric Le Goater     /*
12302da95fd8SCédric Le Goater      * The container memory region representing the address space
12312da95fd8SCédric Le Goater      * window in which the flash modules are mapped. The size and
12322da95fd8SCédric Le Goater      * address depends on the SoC model and controller type.
1233924ed163SCédric Le Goater      */
1234fc664254SCédric Le Goater     memory_region_init(&s->mmio_flash_container, OBJECT(s),
1235fc664254SCédric Le Goater                        TYPE_ASPEED_SMC ".container",
1236fc664254SCédric Le Goater                        asc->flash_window_size);
1237fc664254SCédric Le Goater     sysbus_init_mmio(sbd, &s->mmio_flash_container);
1238fc664254SCédric Le Goater 
1239924ed163SCédric Le Goater     memory_region_init_io(&s->mmio_flash, OBJECT(s),
1240d0180a3aSCédric Le Goater                           &aspeed_smc_flash_default_ops, s,
1241d0180a3aSCédric Le Goater                           TYPE_ASPEED_SMC ".flash",
124230b6852cSCédric Le Goater                           asc->flash_window_size);
1243fc664254SCédric Le Goater     memory_region_add_subregion(&s->mmio_flash_container, 0x0,
1244fc664254SCédric Le Goater                                 &s->mmio_flash);
1245924ed163SCédric Le Goater 
12462da95fd8SCédric Le Goater     /*
12475ade579bSPhilippe Mathieu-Daudé      * Let's create a sub memory region for each possible peripheral. All
12482da95fd8SCédric Le Goater      * have a configurable memory segment in the overall flash mapping
12492da95fd8SCédric Le Goater      * window of the controller but, there is not necessarily a flash
12502da95fd8SCédric Le Goater      * module behind to handle the memory accesses. This depends on
12512da95fd8SCédric Le Goater      * the board configuration.
12522da95fd8SCédric Le Goater      */
1253ae945a00SCédric Le Goater     for (i = 0; i < asc->cs_num_max; ++i) {
1254924ed163SCédric Le Goater         AspeedSMCFlash *fl = &s->flashes[i];
1255924ed163SCédric Le Goater 
1256f75b5331SCédric Le Goater         if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s),
1257f75b5331SCédric Le Goater                                       errp)) {
1258f75b5331SCédric Le Goater             return;
1259f75b5331SCédric Le Goater         }
1260f75b5331SCédric Le Goater         if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) {
1261f75b5331SCédric Le Goater             return;
1262f75b5331SCédric Le Goater         }
1263f75b5331SCédric Le Goater         if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) {
1264f75b5331SCédric Le Goater             return;
1265f75b5331SCédric Le Goater         }
1266924ed163SCédric Le Goater 
1267924ed163SCédric Le Goater         memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
12686bb55e79SCédric Le Goater         offset += asc->segments[i].size;
1269924ed163SCédric Le Goater     }
1270c4e1f0b4SCédric Le Goater 
1271c4e1f0b4SCédric Le Goater     /* DMA support */
127230b6852cSCédric Le Goater     if (aspeed_smc_has_dma(asc)) {
1273c4e1f0b4SCédric Le Goater         aspeed_smc_dma_setup(s, errp);
1274c4e1f0b4SCédric Le Goater     }
12757c1c69bcSCédric Le Goater }
12767c1c69bcSCédric Le Goater 
12777c1c69bcSCédric Le Goater static const VMStateDescription vmstate_aspeed_smc = {
12787c1c69bcSCédric Le Goater     .name = "aspeed.smc",
127905d501a1SJamin Lin     .version_id = 3,
1280f95c4bffSCédric Le Goater     .minimum_version_id = 2,
12810aa6c7dfSRichard Henderson     .fields = (const VMStateField[]) {
12827c1c69bcSCédric Le Goater         VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
1283f95c4bffSCédric Le Goater         VMSTATE_UINT8(snoop_index, AspeedSMCState),
1284f95c4bffSCédric Le Goater         VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
128505d501a1SJamin Lin         VMSTATE_BOOL_V(unselect, AspeedSMCState, 3),
12867c1c69bcSCédric Le Goater         VMSTATE_END_OF_LIST()
12877c1c69bcSCédric Le Goater     }
12887c1c69bcSCédric Le Goater };
12897c1c69bcSCédric Le Goater 
1290dc418eb2SRichard Henderson static const Property aspeed_smc_properties[] = {
12915258c2a6SCédric Le Goater     DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1292ee48fef0SCédric Le Goater     DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
1293c4e1f0b4SCédric Le Goater     DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
1294c4e1f0b4SCédric Le Goater                      TYPE_MEMORY_REGION, MemoryRegion *),
12957c1c69bcSCédric Le Goater };
12967c1c69bcSCédric Le Goater 
aspeed_smc_class_init(ObjectClass * klass,const void * data)129712d1a768SPhilippe Mathieu-Daudé static void aspeed_smc_class_init(ObjectClass *klass, const void *data)
12987c1c69bcSCédric Le Goater {
12997c1c69bcSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
13007c1c69bcSCédric Le Goater 
13017c1c69bcSCédric Le Goater     dc->realize = aspeed_smc_realize;
1302e3d08143SPeter Maydell     device_class_set_legacy_reset(dc, aspeed_smc_reset);
13034f67d30bSMarc-André Lureau     device_class_set_props(dc, aspeed_smc_properties);
13047c1c69bcSCédric Le Goater     dc->vmsd = &vmstate_aspeed_smc;
13057c1c69bcSCédric Le Goater }
13067c1c69bcSCédric Le Goater 
13077c1c69bcSCédric Le Goater static const TypeInfo aspeed_smc_info = {
13087c1c69bcSCédric Le Goater     .name           = TYPE_ASPEED_SMC,
13097c1c69bcSCédric Le Goater     .parent         = TYPE_SYS_BUS_DEVICE,
1310f75b5331SCédric Le Goater     .instance_init  = aspeed_smc_instance_init,
13117c1c69bcSCédric Le Goater     .instance_size  = sizeof(AspeedSMCState),
13127c1c69bcSCédric Le Goater     .class_size     = sizeof(AspeedSMCClass),
131330b6852cSCédric Le Goater     .class_init     = aspeed_smc_class_init,
13147c1c69bcSCédric Le Goater     .abstract       = true,
13157c1c69bcSCédric Le Goater };
13167c1c69bcSCédric Le Goater 
aspeed_smc_flash_realize(DeviceState * dev,Error ** errp)1317f75b5331SCédric Le Goater static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
1318f75b5331SCédric Le Goater {
1319f75b5331SCédric Le Goater     AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
1320f75b5331SCédric Le Goater     g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
1321f75b5331SCédric Le Goater 
1322f75b5331SCédric Le Goater     if (!s->controller) {
1323f75b5331SCédric Le Goater         error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set");
1324f75b5331SCédric Le Goater         return;
1325f75b5331SCédric Le Goater     }
1326f75b5331SCédric Le Goater 
1327b84a9482SCédric Le Goater     s->asc = ASPEED_SMC_GET_CLASS(s->controller);
1328f75b5331SCédric Le Goater 
1329f75b5331SCédric Le Goater     /*
1330f75b5331SCédric Le Goater      * Use the default segment value to size the memory region. This
1331f75b5331SCédric Le Goater      * can be changed by FW at runtime.
1332f75b5331SCédric Le Goater      */
13330559e606SJamin Lin     memory_region_init_io(&s->mmio, OBJECT(s), s->asc->reg_ops,
1334b84a9482SCédric Le Goater                           s, name, s->asc->segments[s->cs].size);
1335f75b5331SCédric Le Goater     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
1336f75b5331SCédric Le Goater }
1337f75b5331SCédric Le Goater 
1338dc418eb2SRichard Henderson static const Property aspeed_smc_flash_properties[] = {
1339f75b5331SCédric Le Goater     DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1340f75b5331SCédric Le Goater     DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC,
1341f75b5331SCédric Le Goater                      AspeedSMCState *),
1342f75b5331SCédric Le Goater };
1343f75b5331SCédric Le Goater 
aspeed_smc_flash_class_init(ObjectClass * klass,const void * data)134412d1a768SPhilippe Mathieu-Daudé static void aspeed_smc_flash_class_init(ObjectClass *klass, const void *data)
1345f75b5331SCédric Le Goater {
1346f75b5331SCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
1347f75b5331SCédric Le Goater 
1348f75b5331SCédric Le Goater     dc->desc = "Aspeed SMC Flash device region";
1349f75b5331SCédric Le Goater     dc->realize = aspeed_smc_flash_realize;
1350f75b5331SCédric Le Goater     device_class_set_props(dc, aspeed_smc_flash_properties);
1351f75b5331SCédric Le Goater }
1352f75b5331SCédric Le Goater 
1353f75b5331SCédric Le Goater static const TypeInfo aspeed_smc_flash_info = {
1354f75b5331SCédric Le Goater     .name           = TYPE_ASPEED_SMC_FLASH,
1355f75b5331SCédric Le Goater     .parent         = TYPE_SYS_BUS_DEVICE,
1356f75b5331SCédric Le Goater     .instance_size  = sizeof(AspeedSMCFlash),
1357f75b5331SCédric Le Goater     .class_init     = aspeed_smc_flash_class_init,
1358f75b5331SCédric Le Goater };
135930b6852cSCédric Le Goater 
136030b6852cSCédric Le Goater /*
136130b6852cSCédric Le Goater  * The Segment Registers of the AST2400 and AST2500 have a 8MB
136230b6852cSCédric Le Goater  * unit. The address range of a flash SPI peripheral is encoded with
136330b6852cSCédric Le Goater  * absolute addresses which should be part of the overall controller
136430b6852cSCédric Le Goater  * window.
136530b6852cSCédric Le Goater  */
aspeed_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)136630b6852cSCédric Le Goater static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
136730b6852cSCédric Le Goater                                           const AspeedSegments *seg)
136830b6852cSCédric Le Goater {
136930b6852cSCédric Le Goater     uint32_t reg = 0;
137030b6852cSCédric Le Goater     reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
137130b6852cSCédric Le Goater     reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
137230b6852cSCédric Le Goater     return reg;
137330b6852cSCédric Le Goater }
137430b6852cSCédric Le Goater 
aspeed_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)137530b6852cSCédric Le Goater static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
137630b6852cSCédric Le Goater                                       uint32_t reg, AspeedSegments *seg)
137730b6852cSCédric Le Goater {
137830b6852cSCédric Le Goater     seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
137930b6852cSCédric Le Goater     seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
138030b6852cSCédric Le Goater }
138130b6852cSCédric Le Goater 
138230b6852cSCédric Le Goater static const AspeedSegments aspeed_2400_smc_segments[] = {
138330b6852cSCédric Le Goater     { 0x10000000, 32 * MiB },
138430b6852cSCédric Le Goater };
138530b6852cSCédric Le Goater 
aspeed_2400_smc_class_init(ObjectClass * klass,const void * data)138612d1a768SPhilippe Mathieu-Daudé static void aspeed_2400_smc_class_init(ObjectClass *klass, const void *data)
138730b6852cSCédric Le Goater {
138830b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
138930b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
139030b6852cSCédric Le Goater 
139130b6852cSCédric Le Goater     dc->desc               = "Aspeed 2400 SMC Controller";
139230b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
139330b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
139430b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
139530b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
139630b6852cSCédric Le Goater     asc->nregs_timings     = 1;
139730b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1398ae945a00SCédric Le Goater     asc->cs_num_max        = 1;
139930b6852cSCédric Le Goater     asc->segments          = aspeed_2400_smc_segments;
140030b6852cSCédric Le Goater     asc->flash_window_base = 0x10000000;
140130b6852cSCédric Le Goater     asc->flash_window_size = 0x6000000;
140230b6852cSCédric Le Goater     asc->features          = 0x0;
140330b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_SMC_MAX;
140430b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_smc_segment_to_reg;
140530b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_smc_reg_to_segment;
140630b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_smc_dma_ctrl;
14070559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
140830b6852cSCédric Le Goater }
140930b6852cSCédric Le Goater 
141030b6852cSCédric Le Goater static const TypeInfo aspeed_2400_smc_info = {
141130b6852cSCédric Le Goater     .name =  "aspeed.smc-ast2400",
141230b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
141330b6852cSCédric Le Goater     .class_init = aspeed_2400_smc_class_init,
141430b6852cSCédric Le Goater };
141530b6852cSCédric Le Goater 
141671255c48SCédric Le Goater static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = {
141771255c48SCédric Le Goater     /*
141871255c48SCédric Le Goater      * CE0 and CE1 types are HW strapped in SCU70. Do it here to
141971255c48SCédric Le Goater      * simplify the model.
142071255c48SCédric Le Goater      */
142171255c48SCédric Le Goater     [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0,
142271255c48SCédric Le Goater };
142371255c48SCédric Le Goater 
142430b6852cSCédric Le Goater static const AspeedSegments aspeed_2400_fmc_segments[] = {
142530b6852cSCédric Le Goater     { 0x20000000, 64 * MiB }, /* start address is readonly */
142630b6852cSCédric Le Goater     { 0x24000000, 32 * MiB },
142730b6852cSCédric Le Goater     { 0x26000000, 32 * MiB },
142830b6852cSCédric Le Goater     { 0x28000000, 32 * MiB },
142930b6852cSCédric Le Goater     { 0x2A000000, 32 * MiB }
143030b6852cSCédric Le Goater };
143130b6852cSCédric Le Goater 
aspeed_2400_fmc_class_init(ObjectClass * klass,const void * data)143212d1a768SPhilippe Mathieu-Daudé static void aspeed_2400_fmc_class_init(ObjectClass *klass, const void *data)
143330b6852cSCédric Le Goater {
143430b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
143530b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
143630b6852cSCédric Le Goater 
143730b6852cSCédric Le Goater     dc->desc               = "Aspeed 2400 FMC Controller";
143830b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
143930b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
144030b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
144130b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
144230b6852cSCédric Le Goater     asc->nregs_timings     = 1;
144330b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1444ae945a00SCédric Le Goater     asc->cs_num_max        = 5;
144530b6852cSCédric Le Goater     asc->segments          = aspeed_2400_fmc_segments;
14467c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0xffff0000;
144771255c48SCédric Le Goater     asc->resets            = aspeed_2400_fmc_resets;
144830b6852cSCédric Le Goater     asc->flash_window_base = 0x20000000;
144930b6852cSCédric Le Goater     asc->flash_window_size = 0x10000000;
145030b6852cSCédric Le Goater     asc->features          = ASPEED_SMC_FEATURE_DMA;
145130b6852cSCédric Le Goater     asc->dma_flash_mask    = 0x0FFFFFFC;
145230b6852cSCédric Le Goater     asc->dma_dram_mask     = 0x1FFFFFFC;
14533a6c0f0eSJamin Lin     asc->dma_start_length  = 4;
145430b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
145530b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_smc_segment_to_reg;
145630b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_smc_reg_to_segment;
145730b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_smc_dma_ctrl;
14580559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
145930b6852cSCédric Le Goater }
146030b6852cSCédric Le Goater 
146130b6852cSCédric Le Goater static const TypeInfo aspeed_2400_fmc_info = {
146230b6852cSCédric Le Goater     .name =  "aspeed.fmc-ast2400",
146330b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
146430b6852cSCédric Le Goater     .class_init = aspeed_2400_fmc_class_init,
146530b6852cSCédric Le Goater };
146630b6852cSCédric Le Goater 
146730b6852cSCédric Le Goater static const AspeedSegments aspeed_2400_spi1_segments[] = {
146830b6852cSCédric Le Goater     { 0x30000000, 64 * MiB },
146930b6852cSCédric Le Goater };
147030b6852cSCédric Le Goater 
aspeed_2400_spi1_addr_width(const AspeedSMCState * s)1471a779e37cSCédric Le Goater static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s)
1472a779e37cSCédric Le Goater {
1473a779e37cSCédric Le Goater     return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3;
1474a779e37cSCédric Le Goater }
1475a779e37cSCédric Le Goater 
aspeed_2400_spi1_class_init(ObjectClass * klass,const void * data)147612d1a768SPhilippe Mathieu-Daudé static void aspeed_2400_spi1_class_init(ObjectClass *klass, const void *data)
147730b6852cSCédric Le Goater {
147830b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
147930b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
148030b6852cSCédric Le Goater 
148130b6852cSCédric Le Goater     dc->desc               = "Aspeed 2400 SPI1 Controller";
148230b6852cSCédric Le Goater     asc->r_conf            = R_SPI_CONF;
148330b6852cSCédric Le Goater     asc->r_ce_ctrl         = 0xff;
148430b6852cSCédric Le Goater     asc->r_ctrl0           = R_SPI_CTRL0;
148530b6852cSCédric Le Goater     asc->r_timings         = R_SPI_TIMINGS;
148630b6852cSCédric Le Goater     asc->nregs_timings     = 1;
148730b6852cSCédric Le Goater     asc->conf_enable_w0    = SPI_CONF_ENABLE_W0;
1488ae945a00SCédric Le Goater     asc->cs_num_max        = 1;
148930b6852cSCédric Le Goater     asc->segments          = aspeed_2400_spi1_segments;
149030b6852cSCédric Le Goater     asc->flash_window_base = 0x30000000;
149130b6852cSCédric Le Goater     asc->flash_window_size = 0x10000000;
149230b6852cSCédric Le Goater     asc->features          = 0x0;
149330b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_SPI_MAX;
149430b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_smc_segment_to_reg;
149530b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_smc_reg_to_segment;
149630b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_smc_dma_ctrl;
1497a779e37cSCédric Le Goater     asc->addr_width        = aspeed_2400_spi1_addr_width;
14980559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
149930b6852cSCédric Le Goater }
150030b6852cSCédric Le Goater 
150130b6852cSCédric Le Goater static const TypeInfo aspeed_2400_spi1_info = {
150230b6852cSCédric Le Goater     .name =  "aspeed.spi1-ast2400",
150330b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
150430b6852cSCédric Le Goater     .class_init = aspeed_2400_spi1_class_init,
150530b6852cSCédric Le Goater };
150630b6852cSCédric Le Goater 
150771255c48SCédric Le Goater static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = {
150871255c48SCédric Le Goater     [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
150971255c48SCédric Le Goater                 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
151071255c48SCédric Le Goater };
151171255c48SCédric Le Goater 
151230b6852cSCédric Le Goater static const AspeedSegments aspeed_2500_fmc_segments[] = {
151330b6852cSCédric Le Goater     { 0x20000000, 128 * MiB }, /* start address is readonly */
151430b6852cSCédric Le Goater     { 0x28000000,  32 * MiB },
151530b6852cSCédric Le Goater     { 0x2A000000,  32 * MiB },
151630b6852cSCédric Le Goater };
151730b6852cSCédric Le Goater 
aspeed_2500_fmc_class_init(ObjectClass * klass,const void * data)151812d1a768SPhilippe Mathieu-Daudé static void aspeed_2500_fmc_class_init(ObjectClass *klass, const void *data)
151930b6852cSCédric Le Goater {
152030b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
152130b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
152230b6852cSCédric Le Goater 
1523d108dfeaSJamin Lin     dc->desc               = "Aspeed 2500 FMC Controller";
152430b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
152530b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
152630b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
152730b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
152830b6852cSCédric Le Goater     asc->nregs_timings     = 1;
152930b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1530ae945a00SCédric Le Goater     asc->cs_num_max        = 3;
153130b6852cSCédric Le Goater     asc->segments          = aspeed_2500_fmc_segments;
15327c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0xffff0000;
153371255c48SCédric Le Goater     asc->resets            = aspeed_2500_fmc_resets;
153430b6852cSCédric Le Goater     asc->flash_window_base = 0x20000000;
153530b6852cSCédric Le Goater     asc->flash_window_size = 0x10000000;
153630b6852cSCédric Le Goater     asc->features          = ASPEED_SMC_FEATURE_DMA;
153730b6852cSCédric Le Goater     asc->dma_flash_mask    = 0x0FFFFFFC;
153830b6852cSCédric Le Goater     asc->dma_dram_mask     = 0x3FFFFFFC;
15393a6c0f0eSJamin Lin     asc->dma_start_length  = 4;
154030b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
154130b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_smc_segment_to_reg;
154230b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_smc_reg_to_segment;
154330b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_smc_dma_ctrl;
15440559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
154530b6852cSCédric Le Goater }
154630b6852cSCédric Le Goater 
154730b6852cSCédric Le Goater static const TypeInfo aspeed_2500_fmc_info = {
154830b6852cSCédric Le Goater     .name =  "aspeed.fmc-ast2500",
154930b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
155030b6852cSCédric Le Goater     .class_init = aspeed_2500_fmc_class_init,
155130b6852cSCédric Le Goater };
155230b6852cSCédric Le Goater 
155330b6852cSCédric Le Goater static const AspeedSegments aspeed_2500_spi1_segments[] = {
155430b6852cSCédric Le Goater     { 0x30000000, 32 * MiB }, /* start address is readonly */
155530b6852cSCédric Le Goater     { 0x32000000, 96 * MiB }, /* end address is readonly */
155630b6852cSCédric Le Goater };
155730b6852cSCédric Le Goater 
aspeed_2500_spi1_class_init(ObjectClass * klass,const void * data)155812d1a768SPhilippe Mathieu-Daudé static void aspeed_2500_spi1_class_init(ObjectClass *klass, const void *data)
155930b6852cSCédric Le Goater {
156030b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
156130b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
156230b6852cSCédric Le Goater 
1563d108dfeaSJamin Lin     dc->desc               = "Aspeed 2500 SPI1 Controller";
156430b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
156530b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
156630b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
156730b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
156830b6852cSCédric Le Goater     asc->nregs_timings     = 1;
156930b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1570ae945a00SCédric Le Goater     asc->cs_num_max        = 2;
157130b6852cSCédric Le Goater     asc->segments          = aspeed_2500_spi1_segments;
15727c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0xffff0000;
157330b6852cSCédric Le Goater     asc->flash_window_base = 0x30000000;
157430b6852cSCédric Le Goater     asc->flash_window_size = 0x8000000;
157530b6852cSCédric Le Goater     asc->features          = 0x0;
157630b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
157730b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_smc_segment_to_reg;
157830b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_smc_reg_to_segment;
157930b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_smc_dma_ctrl;
15800559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
158130b6852cSCédric Le Goater }
158230b6852cSCédric Le Goater 
158330b6852cSCédric Le Goater static const TypeInfo aspeed_2500_spi1_info = {
158430b6852cSCédric Le Goater     .name =  "aspeed.spi1-ast2500",
158530b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
158630b6852cSCédric Le Goater     .class_init = aspeed_2500_spi1_class_init,
158730b6852cSCédric Le Goater };
158830b6852cSCédric Le Goater 
158930b6852cSCédric Le Goater static const AspeedSegments aspeed_2500_spi2_segments[] = {
159030b6852cSCédric Le Goater     { 0x38000000, 32 * MiB }, /* start address is readonly */
159130b6852cSCédric Le Goater     { 0x3A000000, 96 * MiB }, /* end address is readonly */
159230b6852cSCédric Le Goater };
159330b6852cSCédric Le Goater 
aspeed_2500_spi2_class_init(ObjectClass * klass,const void * data)159412d1a768SPhilippe Mathieu-Daudé static void aspeed_2500_spi2_class_init(ObjectClass *klass, const void *data)
159530b6852cSCédric Le Goater {
159630b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
159730b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
159830b6852cSCédric Le Goater 
1599d108dfeaSJamin Lin     dc->desc               = "Aspeed 2500 SPI2 Controller";
160030b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
160130b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
160230b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
160330b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
160430b6852cSCédric Le Goater     asc->nregs_timings     = 1;
160530b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1606ae945a00SCédric Le Goater     asc->cs_num_max        = 2;
160730b6852cSCédric Le Goater     asc->segments          = aspeed_2500_spi2_segments;
16087c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0xffff0000;
160930b6852cSCédric Le Goater     asc->flash_window_base = 0x38000000;
161030b6852cSCédric Le Goater     asc->flash_window_size = 0x8000000;
161130b6852cSCédric Le Goater     asc->features          = 0x0;
161230b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
161330b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_smc_segment_to_reg;
161430b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_smc_reg_to_segment;
161530b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_smc_dma_ctrl;
16160559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
161730b6852cSCédric Le Goater }
161830b6852cSCédric Le Goater 
161930b6852cSCédric Le Goater static const TypeInfo aspeed_2500_spi2_info = {
162030b6852cSCédric Le Goater     .name =  "aspeed.spi2-ast2500",
162130b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
162230b6852cSCédric Le Goater     .class_init = aspeed_2500_spi2_class_init,
162330b6852cSCédric Le Goater };
162430b6852cSCédric Le Goater 
162530b6852cSCédric Le Goater /*
162630b6852cSCédric Le Goater  * The Segment Registers of the AST2600 have a 1MB unit. The address
162730b6852cSCédric Le Goater  * range of a flash SPI peripheral is encoded with offsets in the overall
162830b6852cSCédric Le Goater  * controller window. The previous SoC AST2400 and AST2500 used
162930b6852cSCédric Le Goater  * absolute addresses. Only bits [27:20] are relevant and the end
163030b6852cSCédric Le Goater  * address is an upper bound limit.
163130b6852cSCédric Le Goater  */
163230b6852cSCédric Le Goater #define AST2600_SEG_ADDR_MASK 0x0ff00000
163330b6852cSCédric Le Goater 
aspeed_2600_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)163430b6852cSCédric Le Goater static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
163530b6852cSCédric Le Goater                                                const AspeedSegments *seg)
163630b6852cSCédric Le Goater {
163730b6852cSCédric Le Goater     uint32_t reg = 0;
163830b6852cSCédric Le Goater 
163930b6852cSCédric Le Goater     /* Disabled segments have a nil register */
164030b6852cSCédric Le Goater     if (!seg->size) {
164130b6852cSCédric Le Goater         return 0;
164230b6852cSCédric Le Goater     }
164330b6852cSCédric Le Goater 
164430b6852cSCédric Le Goater     reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */
164530b6852cSCédric Le Goater     reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */
164630b6852cSCédric Le Goater     return reg;
164730b6852cSCédric Le Goater }
164830b6852cSCédric Le Goater 
aspeed_2600_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)164930b6852cSCédric Le Goater static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
165030b6852cSCédric Le Goater                                            uint32_t reg, AspeedSegments *seg)
165130b6852cSCédric Le Goater {
165230b6852cSCédric Le Goater     uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
165330b6852cSCédric Le Goater     uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
165430b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
165530b6852cSCédric Le Goater 
165630b6852cSCédric Le Goater     if (reg) {
165730b6852cSCédric Le Goater         seg->addr = asc->flash_window_base + start_offset;
165830b6852cSCédric Le Goater         seg->size = end_offset + MiB - start_offset;
165930b6852cSCédric Le Goater     } else {
166030b6852cSCédric Le Goater         seg->addr = asc->flash_window_base;
166130b6852cSCédric Le Goater         seg->size = 0;
166230b6852cSCédric Le Goater     }
166330b6852cSCédric Le Goater }
166430b6852cSCédric Le Goater 
166571255c48SCédric Le Goater static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = {
166671255c48SCédric Le Goater     [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
166771255c48SCédric Le Goater                 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 |
166871255c48SCédric Le Goater                 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2),
166971255c48SCédric Le Goater };
167071255c48SCédric Le Goater 
167130b6852cSCédric Le Goater static const AspeedSegments aspeed_2600_fmc_segments[] = {
167230b6852cSCédric Le Goater     { 0x0, 128 * MiB }, /* start address is readonly */
167330b6852cSCédric Le Goater     { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
167430b6852cSCédric Le Goater     { 0x0, 0 }, /* disabled */
167530b6852cSCédric Le Goater };
167630b6852cSCédric Le Goater 
aspeed_2600_fmc_class_init(ObjectClass * klass,const void * data)167712d1a768SPhilippe Mathieu-Daudé static void aspeed_2600_fmc_class_init(ObjectClass *klass, const void *data)
167830b6852cSCédric Le Goater {
167930b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
168030b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
168130b6852cSCédric Le Goater 
168230b6852cSCédric Le Goater     dc->desc               = "Aspeed 2600 FMC Controller";
168330b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
168430b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
168530b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
168630b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
168730b6852cSCédric Le Goater     asc->nregs_timings     = 1;
168830b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1689ae945a00SCédric Le Goater     asc->cs_num_max        = 3;
169030b6852cSCédric Le Goater     asc->segments          = aspeed_2600_fmc_segments;
16917c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0x0ff00ff0;
169271255c48SCédric Le Goater     asc->resets            = aspeed_2600_fmc_resets;
169330b6852cSCédric Le Goater     asc->flash_window_base = 0x20000000;
169430b6852cSCédric Le Goater     asc->flash_window_size = 0x10000000;
169530b6852cSCédric Le Goater     asc->features          = ASPEED_SMC_FEATURE_DMA |
169630b6852cSCédric Le Goater                              ASPEED_SMC_FEATURE_WDT_CONTROL;
169730b6852cSCédric Le Goater     asc->dma_flash_mask    = 0x0FFFFFFC;
169830b6852cSCédric Le Goater     asc->dma_dram_mask     = 0x3FFFFFFC;
16993a6c0f0eSJamin Lin     asc->dma_start_length  = 1;
170030b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
170130b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_2600_smc_segment_to_reg;
170230b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_2600_smc_reg_to_segment;
170330b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
17040559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
170530b6852cSCédric Le Goater }
170630b6852cSCédric Le Goater 
170730b6852cSCédric Le Goater static const TypeInfo aspeed_2600_fmc_info = {
170830b6852cSCédric Le Goater     .name =  "aspeed.fmc-ast2600",
170930b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
171030b6852cSCédric Le Goater     .class_init = aspeed_2600_fmc_class_init,
171130b6852cSCédric Le Goater };
171230b6852cSCédric Le Goater 
171330b6852cSCédric Le Goater static const AspeedSegments aspeed_2600_spi1_segments[] = {
171430b6852cSCédric Le Goater     { 0x0, 128 * MiB }, /* start address is readonly */
171530b6852cSCédric Le Goater     { 0x0, 0 }, /* disabled */
171630b6852cSCédric Le Goater };
171730b6852cSCédric Le Goater 
aspeed_2600_spi1_class_init(ObjectClass * klass,const void * data)171812d1a768SPhilippe Mathieu-Daudé static void aspeed_2600_spi1_class_init(ObjectClass *klass, const void *data)
171930b6852cSCédric Le Goater {
172030b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
172130b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
172230b6852cSCédric Le Goater 
172330b6852cSCédric Le Goater     dc->desc               = "Aspeed 2600 SPI1 Controller";
172430b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
172530b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
172630b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
172730b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
172830b6852cSCédric Le Goater     asc->nregs_timings     = 2;
172930b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1730ae945a00SCédric Le Goater     asc->cs_num_max        = 2;
173130b6852cSCédric Le Goater     asc->segments          = aspeed_2600_spi1_segments;
17327c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0x0ff00ff0;
173330b6852cSCédric Le Goater     asc->flash_window_base = 0x30000000;
173430b6852cSCédric Le Goater     asc->flash_window_size = 0x10000000;
173530b6852cSCédric Le Goater     asc->features          = ASPEED_SMC_FEATURE_DMA |
173630b6852cSCédric Le Goater                              ASPEED_SMC_FEATURE_DMA_GRANT;
173730b6852cSCédric Le Goater     asc->dma_flash_mask    = 0x0FFFFFFC;
173830b6852cSCédric Le Goater     asc->dma_dram_mask     = 0x3FFFFFFC;
17393a6c0f0eSJamin Lin     asc->dma_start_length  = 1;
174030b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
174130b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_2600_smc_segment_to_reg;
174230b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_2600_smc_reg_to_segment;
174330b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
17440559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
174530b6852cSCédric Le Goater }
174630b6852cSCédric Le Goater 
174730b6852cSCédric Le Goater static const TypeInfo aspeed_2600_spi1_info = {
174830b6852cSCédric Le Goater     .name =  "aspeed.spi1-ast2600",
174930b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
175030b6852cSCédric Le Goater     .class_init = aspeed_2600_spi1_class_init,
175130b6852cSCédric Le Goater };
175230b6852cSCédric Le Goater 
175330b6852cSCédric Le Goater static const AspeedSegments aspeed_2600_spi2_segments[] = {
175430b6852cSCédric Le Goater     { 0x0, 128 * MiB }, /* start address is readonly */
175530b6852cSCédric Le Goater     { 0x0, 0 }, /* disabled */
175630b6852cSCédric Le Goater     { 0x0, 0 }, /* disabled */
175730b6852cSCédric Le Goater };
175830b6852cSCédric Le Goater 
aspeed_2600_spi2_class_init(ObjectClass * klass,const void * data)175912d1a768SPhilippe Mathieu-Daudé static void aspeed_2600_spi2_class_init(ObjectClass *klass, const void *data)
176030b6852cSCédric Le Goater {
176130b6852cSCédric Le Goater     DeviceClass *dc = DEVICE_CLASS(klass);
176230b6852cSCédric Le Goater     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
176330b6852cSCédric Le Goater 
176430b6852cSCédric Le Goater     dc->desc               = "Aspeed 2600 SPI2 Controller";
176530b6852cSCédric Le Goater     asc->r_conf            = R_CONF;
176630b6852cSCédric Le Goater     asc->r_ce_ctrl         = R_CE_CTRL;
176730b6852cSCédric Le Goater     asc->r_ctrl0           = R_CTRL0;
176830b6852cSCédric Le Goater     asc->r_timings         = R_TIMINGS;
176930b6852cSCédric Le Goater     asc->nregs_timings     = 3;
177030b6852cSCédric Le Goater     asc->conf_enable_w0    = CONF_ENABLE_W0;
1771ae945a00SCédric Le Goater     asc->cs_num_max        = 3;
177230b6852cSCédric Le Goater     asc->segments          = aspeed_2600_spi2_segments;
17737c8d2fc4SCédric Le Goater     asc->segment_addr_mask = 0x0ff00ff0;
177430b6852cSCédric Le Goater     asc->flash_window_base = 0x50000000;
177530b6852cSCédric Le Goater     asc->flash_window_size = 0x10000000;
177630b6852cSCédric Le Goater     asc->features          = ASPEED_SMC_FEATURE_DMA |
177730b6852cSCédric Le Goater                              ASPEED_SMC_FEATURE_DMA_GRANT;
177830b6852cSCédric Le Goater     asc->dma_flash_mask    = 0x0FFFFFFC;
177930b6852cSCédric Le Goater     asc->dma_dram_mask     = 0x3FFFFFFC;
17803a6c0f0eSJamin Lin     asc->dma_start_length  = 1;
178130b6852cSCédric Le Goater     asc->nregs             = ASPEED_SMC_R_MAX;
178230b6852cSCédric Le Goater     asc->segment_to_reg    = aspeed_2600_smc_segment_to_reg;
178330b6852cSCédric Le Goater     asc->reg_to_segment    = aspeed_2600_smc_reg_to_segment;
178430b6852cSCédric Le Goater     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
17850559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
178630b6852cSCédric Le Goater }
178730b6852cSCédric Le Goater 
178830b6852cSCédric Le Goater static const TypeInfo aspeed_2600_spi2_info = {
178930b6852cSCédric Le Goater     .name =  "aspeed.spi2-ast2600",
179030b6852cSCédric Le Goater     .parent = TYPE_ASPEED_SMC,
179130b6852cSCédric Le Goater     .class_init = aspeed_2600_spi2_class_init,
179230b6852cSCédric Le Goater };
179330b6852cSCédric Le Goater 
17942850df6aSSteven Lee /*
17952850df6aSSteven Lee  * The FMC Segment Registers of the AST1030 have a 512KB unit.
17962850df6aSSteven Lee  * Only bits [27:19] are used for decoding.
17972850df6aSSteven Lee  */
17982850df6aSSteven Lee #define AST1030_SEG_ADDR_MASK 0x0ff80000
17992850df6aSSteven Lee 
aspeed_1030_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)18002850df6aSSteven Lee static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s,
18012850df6aSSteven Lee         const AspeedSegments *seg)
18022850df6aSSteven Lee {
18032850df6aSSteven Lee     uint32_t reg = 0;
18042850df6aSSteven Lee 
18052850df6aSSteven Lee     /* Disabled segments have a nil register */
18062850df6aSSteven Lee     if (!seg->size) {
18072850df6aSSteven Lee         return 0;
18082850df6aSSteven Lee     }
18092850df6aSSteven Lee 
18102850df6aSSteven Lee     reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */
18112850df6aSSteven Lee     reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */
18122850df6aSSteven Lee     return reg;
18132850df6aSSteven Lee }
18142850df6aSSteven Lee 
aspeed_1030_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)18152850df6aSSteven Lee static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s,
18162850df6aSSteven Lee         uint32_t reg, AspeedSegments *seg)
18172850df6aSSteven Lee {
18182850df6aSSteven Lee     uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK;
18192850df6aSSteven Lee     uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK;
18202850df6aSSteven Lee     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
18212850df6aSSteven Lee 
18222850df6aSSteven Lee     if (reg) {
18232850df6aSSteven Lee         seg->addr = asc->flash_window_base + start_offset;
18242850df6aSSteven Lee         seg->size = end_offset + (512 * KiB) - start_offset;
18252850df6aSSteven Lee     } else {
18262850df6aSSteven Lee         seg->addr = asc->flash_window_base;
18272850df6aSSteven Lee         seg->size = 0;
18282850df6aSSteven Lee     }
18292850df6aSSteven Lee }
18302850df6aSSteven Lee 
18312850df6aSSteven Lee static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = {
18322850df6aSSteven Lee     [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
18332850df6aSSteven Lee                             CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
18342850df6aSSteven Lee };
18352850df6aSSteven Lee 
18362850df6aSSteven Lee static const AspeedSegments aspeed_1030_fmc_segments[] = {
18372850df6aSSteven Lee     { 0x0, 128 * MiB }, /* start address is readonly */
18382850df6aSSteven Lee     { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
18392850df6aSSteven Lee     { 0x0, 0 }, /* disabled */
18402850df6aSSteven Lee };
18412850df6aSSteven Lee 
aspeed_1030_fmc_class_init(ObjectClass * klass,const void * data)184212d1a768SPhilippe Mathieu-Daudé static void aspeed_1030_fmc_class_init(ObjectClass *klass, const void *data)
18432850df6aSSteven Lee {
18442850df6aSSteven Lee     DeviceClass *dc = DEVICE_CLASS(klass);
18452850df6aSSteven Lee     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
18462850df6aSSteven Lee 
18472850df6aSSteven Lee     dc->desc               = "Aspeed 1030 FMC Controller";
18482850df6aSSteven Lee     asc->r_conf            = R_CONF;
18492850df6aSSteven Lee     asc->r_ce_ctrl         = R_CE_CTRL;
18502850df6aSSteven Lee     asc->r_ctrl0           = R_CTRL0;
18512850df6aSSteven Lee     asc->r_timings         = R_TIMINGS;
18522850df6aSSteven Lee     asc->nregs_timings     = 2;
18532850df6aSSteven Lee     asc->conf_enable_w0    = CONF_ENABLE_W0;
18542850df6aSSteven Lee     asc->cs_num_max        = 2;
18552850df6aSSteven Lee     asc->segments          = aspeed_1030_fmc_segments;
18562850df6aSSteven Lee     asc->segment_addr_mask = 0x0ff80ff8;
18572850df6aSSteven Lee     asc->resets            = aspeed_1030_fmc_resets;
18582850df6aSSteven Lee     asc->flash_window_base = 0x80000000;
18592850df6aSSteven Lee     asc->flash_window_size = 0x10000000;
18602850df6aSSteven Lee     asc->features          = ASPEED_SMC_FEATURE_DMA;
18612850df6aSSteven Lee     asc->dma_flash_mask    = 0x0FFFFFFC;
18622850df6aSSteven Lee     asc->dma_dram_mask     = 0x000BFFFC;
18633a6c0f0eSJamin Lin     asc->dma_start_length  = 1;
18642850df6aSSteven Lee     asc->nregs             = ASPEED_SMC_R_MAX;
18652850df6aSSteven Lee     asc->segment_to_reg    = aspeed_1030_smc_segment_to_reg;
18662850df6aSSteven Lee     asc->reg_to_segment    = aspeed_1030_smc_reg_to_segment;
18672850df6aSSteven Lee     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
18680559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
18692850df6aSSteven Lee }
18702850df6aSSteven Lee 
18712850df6aSSteven Lee static const TypeInfo aspeed_1030_fmc_info = {
18722850df6aSSteven Lee     .name =  "aspeed.fmc-ast1030",
18732850df6aSSteven Lee     .parent = TYPE_ASPEED_SMC,
18742850df6aSSteven Lee     .class_init = aspeed_1030_fmc_class_init,
18752850df6aSSteven Lee };
18762850df6aSSteven Lee 
18772850df6aSSteven Lee static const AspeedSegments aspeed_1030_spi1_segments[] = {
18782850df6aSSteven Lee     { 0x0, 128 * MiB }, /* start address is readonly */
18792850df6aSSteven Lee     { 0x0, 0 }, /* disabled */
18802850df6aSSteven Lee };
18812850df6aSSteven Lee 
aspeed_1030_spi1_class_init(ObjectClass * klass,const void * data)188212d1a768SPhilippe Mathieu-Daudé static void aspeed_1030_spi1_class_init(ObjectClass *klass, const void *data)
18832850df6aSSteven Lee {
18842850df6aSSteven Lee     DeviceClass *dc = DEVICE_CLASS(klass);
18852850df6aSSteven Lee     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
18862850df6aSSteven Lee 
18872850df6aSSteven Lee     dc->desc               = "Aspeed 1030 SPI1 Controller";
18882850df6aSSteven Lee     asc->r_conf            = R_CONF;
18892850df6aSSteven Lee     asc->r_ce_ctrl         = R_CE_CTRL;
18902850df6aSSteven Lee     asc->r_ctrl0           = R_CTRL0;
18912850df6aSSteven Lee     asc->r_timings         = R_TIMINGS;
18922850df6aSSteven Lee     asc->nregs_timings     = 2;
18932850df6aSSteven Lee     asc->conf_enable_w0    = CONF_ENABLE_W0;
18942850df6aSSteven Lee     asc->cs_num_max        = 2;
18952850df6aSSteven Lee     asc->segments          = aspeed_1030_spi1_segments;
18962850df6aSSteven Lee     asc->segment_addr_mask = 0x0ff00ff0;
18972850df6aSSteven Lee     asc->flash_window_base = 0x90000000;
18982850df6aSSteven Lee     asc->flash_window_size = 0x10000000;
18992850df6aSSteven Lee     asc->features          = ASPEED_SMC_FEATURE_DMA;
19002850df6aSSteven Lee     asc->dma_flash_mask    = 0x0FFFFFFC;
19012850df6aSSteven Lee     asc->dma_dram_mask     = 0x000BFFFC;
19023a6c0f0eSJamin Lin     asc->dma_start_length  = 1;
19032850df6aSSteven Lee     asc->nregs             = ASPEED_SMC_R_MAX;
19042850df6aSSteven Lee     asc->segment_to_reg    = aspeed_2600_smc_segment_to_reg;
19052850df6aSSteven Lee     asc->reg_to_segment    = aspeed_2600_smc_reg_to_segment;
19062850df6aSSteven Lee     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
19070559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
19082850df6aSSteven Lee }
19092850df6aSSteven Lee 
19102850df6aSSteven Lee static const TypeInfo aspeed_1030_spi1_info = {
19112850df6aSSteven Lee     .name =  "aspeed.spi1-ast1030",
19122850df6aSSteven Lee     .parent = TYPE_ASPEED_SMC,
19132850df6aSSteven Lee     .class_init = aspeed_1030_spi1_class_init,
19142850df6aSSteven Lee };
19152850df6aSSteven Lee static const AspeedSegments aspeed_1030_spi2_segments[] = {
19162850df6aSSteven Lee     { 0x0, 128 * MiB }, /* start address is readonly */
19172850df6aSSteven Lee     { 0x0, 0 }, /* disabled */
19182850df6aSSteven Lee };
19192850df6aSSteven Lee 
aspeed_1030_spi2_class_init(ObjectClass * klass,const void * data)192012d1a768SPhilippe Mathieu-Daudé static void aspeed_1030_spi2_class_init(ObjectClass *klass, const void *data)
19212850df6aSSteven Lee {
19222850df6aSSteven Lee     DeviceClass *dc = DEVICE_CLASS(klass);
19232850df6aSSteven Lee     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
19242850df6aSSteven Lee 
19252850df6aSSteven Lee     dc->desc               = "Aspeed 1030 SPI2 Controller";
19262850df6aSSteven Lee     asc->r_conf            = R_CONF;
19272850df6aSSteven Lee     asc->r_ce_ctrl         = R_CE_CTRL;
19282850df6aSSteven Lee     asc->r_ctrl0           = R_CTRL0;
19292850df6aSSteven Lee     asc->r_timings         = R_TIMINGS;
19302850df6aSSteven Lee     asc->nregs_timings     = 2;
19312850df6aSSteven Lee     asc->conf_enable_w0    = CONF_ENABLE_W0;
19322850df6aSSteven Lee     asc->cs_num_max        = 2;
19332850df6aSSteven Lee     asc->segments          = aspeed_1030_spi2_segments;
19342850df6aSSteven Lee     asc->segment_addr_mask = 0x0ff00ff0;
19352850df6aSSteven Lee     asc->flash_window_base = 0xb0000000;
19362850df6aSSteven Lee     asc->flash_window_size = 0x10000000;
19372850df6aSSteven Lee     asc->features          = ASPEED_SMC_FEATURE_DMA;
19382850df6aSSteven Lee     asc->dma_flash_mask    = 0x0FFFFFFC;
19392850df6aSSteven Lee     asc->dma_dram_mask     = 0x000BFFFC;
19403a6c0f0eSJamin Lin     asc->dma_start_length  = 1;
19412850df6aSSteven Lee     asc->nregs             = ASPEED_SMC_R_MAX;
19422850df6aSSteven Lee     asc->segment_to_reg    = aspeed_2600_smc_segment_to_reg;
19432850df6aSSteven Lee     asc->reg_to_segment    = aspeed_2600_smc_reg_to_segment;
19442850df6aSSteven Lee     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
19450559e606SJamin Lin     asc->reg_ops           = &aspeed_smc_flash_ops;
19462850df6aSSteven Lee }
19472850df6aSSteven Lee 
19482850df6aSSteven Lee static const TypeInfo aspeed_1030_spi2_info = {
19492850df6aSSteven Lee     .name =  "aspeed.spi2-ast1030",
19502850df6aSSteven Lee     .parent = TYPE_ASPEED_SMC,
19512850df6aSSteven Lee     .class_init = aspeed_1030_spi2_class_init,
19522850df6aSSteven Lee };
19532850df6aSSteven Lee 
1954bdb3748dSJamin Lin /*
1955bdb3748dSJamin Lin  * The FMC Segment Registers of the AST2700 have a 64KB unit.
1956bdb3748dSJamin Lin  * Only bits [31:16] are used for decoding.
1957bdb3748dSJamin Lin  */
1958bdb3748dSJamin Lin #define AST2700_SEG_ADDR_MASK 0xffff0000
1959bdb3748dSJamin Lin 
aspeed_2700_smc_segment_to_reg(const AspeedSMCState * s,const AspeedSegments * seg)1960bdb3748dSJamin Lin static uint32_t aspeed_2700_smc_segment_to_reg(const AspeedSMCState *s,
1961bdb3748dSJamin Lin                                                const AspeedSegments *seg)
1962bdb3748dSJamin Lin {
1963bdb3748dSJamin Lin     uint32_t reg = 0;
1964bdb3748dSJamin Lin 
1965bdb3748dSJamin Lin     /* Disabled segments have a nil register */
1966bdb3748dSJamin Lin     if (!seg->size) {
1967bdb3748dSJamin Lin         return 0;
1968bdb3748dSJamin Lin     }
1969bdb3748dSJamin Lin 
1970bdb3748dSJamin Lin     reg |= (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */
1971bdb3748dSJamin Lin     reg |= (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end offset */
1972bdb3748dSJamin Lin     return reg;
1973bdb3748dSJamin Lin }
1974bdb3748dSJamin Lin 
aspeed_2700_smc_reg_to_segment(const AspeedSMCState * s,uint32_t reg,AspeedSegments * seg)1975bdb3748dSJamin Lin static void aspeed_2700_smc_reg_to_segment(const AspeedSMCState *s,
1976bdb3748dSJamin Lin                                            uint32_t reg, AspeedSegments *seg)
1977bdb3748dSJamin Lin {
1978bdb3748dSJamin Lin     uint32_t start_offset = (reg << 16) & AST2700_SEG_ADDR_MASK;
1979bdb3748dSJamin Lin     uint32_t end_offset = reg & AST2700_SEG_ADDR_MASK;
1980bdb3748dSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1981bdb3748dSJamin Lin 
1982bdb3748dSJamin Lin     if (reg) {
1983bdb3748dSJamin Lin         seg->addr = asc->flash_window_base + start_offset;
1984bdb3748dSJamin Lin         seg->size = end_offset + (64 * KiB) - start_offset;
1985bdb3748dSJamin Lin     } else {
1986bdb3748dSJamin Lin         seg->addr = asc->flash_window_base;
1987bdb3748dSJamin Lin         seg->size = 0;
1988bdb3748dSJamin Lin     }
1989bdb3748dSJamin Lin }
1990bdb3748dSJamin Lin 
1991bdb3748dSJamin Lin static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] = {
1992bdb3748dSJamin Lin     [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1993bdb3748dSJamin Lin             CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1994bdb3748dSJamin Lin     [R_CE_CTRL] = 0x0000aa00,
1995bdb3748dSJamin Lin     [R_CTRL0] = 0x406b0641,
1996bdb3748dSJamin Lin     [R_CTRL1] = 0x00000400,
1997bdb3748dSJamin Lin     [R_CTRL2] = 0x00000400,
1998bdb3748dSJamin Lin     [R_CTRL3] = 0x00000400,
1999bdb3748dSJamin Lin     [R_SEG_ADDR0] = 0x08000000,
2000bdb3748dSJamin Lin     [R_SEG_ADDR1] = 0x10000800,
2001bdb3748dSJamin Lin     [R_SEG_ADDR2] = 0x00000000,
2002bdb3748dSJamin Lin     [R_SEG_ADDR3] = 0x00000000,
2003bdb3748dSJamin Lin     [R_DUMMY_DATA] = 0x00010000,
2004bdb3748dSJamin Lin     [R_DMA_DRAM_ADDR_HIGH] = 0x00000000,
2005bdb3748dSJamin Lin     [R_TIMINGS] = 0x007b0000,
2006bdb3748dSJamin Lin };
2007bdb3748dSJamin Lin 
2008bdb3748dSJamin Lin static const MemoryRegionOps aspeed_2700_smc_flash_ops = {
2009bdb3748dSJamin Lin     .read = aspeed_smc_flash_read,
2010bdb3748dSJamin Lin     .write = aspeed_smc_flash_write,
2011bdb3748dSJamin Lin     .endianness = DEVICE_LITTLE_ENDIAN,
2012bdb3748dSJamin Lin     .valid = {
2013bdb3748dSJamin Lin         .min_access_size = 1,
2014bdb3748dSJamin Lin         .max_access_size = 8,
2015bdb3748dSJamin Lin     },
2016bdb3748dSJamin Lin };
2017bdb3748dSJamin Lin 
2018bdb3748dSJamin Lin static const AspeedSegments aspeed_2700_fmc_segments[] = {
2019bdb3748dSJamin Lin     { 0x0, 128 * MiB }, /* start address is readonly */
2020bdb3748dSJamin Lin     { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
2021bdb3748dSJamin Lin     { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
2022bdb3748dSJamin Lin     { 0x0, 0 }, /* disabled */
2023bdb3748dSJamin Lin };
2024bdb3748dSJamin Lin 
aspeed_2700_fmc_class_init(ObjectClass * klass,const void * data)202512d1a768SPhilippe Mathieu-Daudé static void aspeed_2700_fmc_class_init(ObjectClass *klass, const void *data)
2026bdb3748dSJamin Lin {
2027bdb3748dSJamin Lin     DeviceClass *dc = DEVICE_CLASS(klass);
2028bdb3748dSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
2029bdb3748dSJamin Lin 
2030bdb3748dSJamin Lin     dc->desc               = "Aspeed 2700 FMC Controller";
2031bdb3748dSJamin Lin     asc->r_conf            = R_CONF;
2032bdb3748dSJamin Lin     asc->r_ce_ctrl         = R_CE_CTRL;
2033bdb3748dSJamin Lin     asc->r_ctrl0           = R_CTRL0;
2034bdb3748dSJamin Lin     asc->r_timings         = R_TIMINGS;
2035bdb3748dSJamin Lin     asc->nregs_timings     = 3;
2036bdb3748dSJamin Lin     asc->conf_enable_w0    = CONF_ENABLE_W0;
2037bdb3748dSJamin Lin     asc->cs_num_max        = 3;
2038bdb3748dSJamin Lin     asc->segments          = aspeed_2700_fmc_segments;
2039bdb3748dSJamin Lin     asc->segment_addr_mask = 0xffffffff;
2040bdb3748dSJamin Lin     asc->resets            = aspeed_2700_fmc_resets;
2041bdb3748dSJamin Lin     asc->flash_window_base = 0x100000000;
2042bdb3748dSJamin Lin     asc->flash_window_size = 1 * GiB;
2043bdb3748dSJamin Lin     asc->features          = ASPEED_SMC_FEATURE_DMA |
2044bdb3748dSJamin Lin                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
2045bdb3748dSJamin Lin     asc->dma_flash_mask    = 0x2FFFFFFC;
2046bdb3748dSJamin Lin     asc->dma_dram_mask     = 0xFFFFFFFC;
2047bdb3748dSJamin Lin     asc->dma_start_length  = 1;
2048bdb3748dSJamin Lin     asc->nregs             = ASPEED_SMC_R_MAX;
2049bdb3748dSJamin Lin     asc->segment_to_reg    = aspeed_2700_smc_segment_to_reg;
2050bdb3748dSJamin Lin     asc->reg_to_segment    = aspeed_2700_smc_reg_to_segment;
2051bdb3748dSJamin Lin     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
2052bdb3748dSJamin Lin     asc->reg_ops           = &aspeed_2700_smc_flash_ops;
2053bdb3748dSJamin Lin }
2054bdb3748dSJamin Lin 
2055bdb3748dSJamin Lin static const TypeInfo aspeed_2700_fmc_info = {
2056bdb3748dSJamin Lin     .name =  "aspeed.fmc-ast2700",
2057bdb3748dSJamin Lin     .parent = TYPE_ASPEED_SMC,
2058bdb3748dSJamin Lin     .class_init = aspeed_2700_fmc_class_init,
2059bdb3748dSJamin Lin };
2060bdb3748dSJamin Lin 
2061bdb3748dSJamin Lin static const AspeedSegments aspeed_2700_spi0_segments[] = {
2062bdb3748dSJamin Lin     { 0x0, 128 * MiB }, /* start address is readonly */
2063bdb3748dSJamin Lin     { 128 * MiB, 128 * MiB }, /* start address is readonly */
2064bdb3748dSJamin Lin     { 0x0, 0 }, /* disabled */
2065bdb3748dSJamin Lin };
2066bdb3748dSJamin Lin 
aspeed_2700_spi0_class_init(ObjectClass * klass,const void * data)206712d1a768SPhilippe Mathieu-Daudé static void aspeed_2700_spi0_class_init(ObjectClass *klass, const void *data)
2068bdb3748dSJamin Lin {
2069bdb3748dSJamin Lin     DeviceClass *dc = DEVICE_CLASS(klass);
2070bdb3748dSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
2071bdb3748dSJamin Lin 
2072bdb3748dSJamin Lin     dc->desc               = "Aspeed 2700 SPI0 Controller";
2073bdb3748dSJamin Lin     asc->r_conf            = R_CONF;
2074bdb3748dSJamin Lin     asc->r_ce_ctrl         = R_CE_CTRL;
2075bdb3748dSJamin Lin     asc->r_ctrl0           = R_CTRL0;
2076bdb3748dSJamin Lin     asc->r_timings         = R_TIMINGS;
2077bdb3748dSJamin Lin     asc->nregs_timings     = 2;
2078bdb3748dSJamin Lin     asc->conf_enable_w0    = CONF_ENABLE_W0;
2079bdb3748dSJamin Lin     asc->cs_num_max        = 2;
2080bdb3748dSJamin Lin     asc->segments          = aspeed_2700_spi0_segments;
2081bdb3748dSJamin Lin     asc->segment_addr_mask = 0xffffffff;
2082bdb3748dSJamin Lin     asc->flash_window_base = 0x180000000;
2083bdb3748dSJamin Lin     asc->flash_window_size = 1 * GiB;
2084bdb3748dSJamin Lin     asc->features          = ASPEED_SMC_FEATURE_DMA |
2085bdb3748dSJamin Lin                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
2086bdb3748dSJamin Lin     asc->dma_flash_mask    = 0x2FFFFFFC;
2087bdb3748dSJamin Lin     asc->dma_dram_mask     = 0xFFFFFFFC;
2088bdb3748dSJamin Lin     asc->dma_start_length  = 1;
2089bdb3748dSJamin Lin     asc->nregs             = ASPEED_SMC_R_MAX;
2090bdb3748dSJamin Lin     asc->segment_to_reg    = aspeed_2700_smc_segment_to_reg;
2091bdb3748dSJamin Lin     asc->reg_to_segment    = aspeed_2700_smc_reg_to_segment;
2092bdb3748dSJamin Lin     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
2093bdb3748dSJamin Lin     asc->reg_ops           = &aspeed_2700_smc_flash_ops;
2094bdb3748dSJamin Lin }
2095bdb3748dSJamin Lin 
2096bdb3748dSJamin Lin static const TypeInfo aspeed_2700_spi0_info = {
2097bdb3748dSJamin Lin     .name =  "aspeed.spi0-ast2700",
2098bdb3748dSJamin Lin     .parent = TYPE_ASPEED_SMC,
2099bdb3748dSJamin Lin     .class_init = aspeed_2700_spi0_class_init,
2100bdb3748dSJamin Lin };
2101bdb3748dSJamin Lin 
2102bdb3748dSJamin Lin static const AspeedSegments aspeed_2700_spi1_segments[] = {
2103bdb3748dSJamin Lin     { 0x0, 128 * MiB }, /* start address is readonly */
2104bdb3748dSJamin Lin     { 0x0, 0 }, /* disabled */
2105bdb3748dSJamin Lin };
2106bdb3748dSJamin Lin 
aspeed_2700_spi1_class_init(ObjectClass * klass,const void * data)210712d1a768SPhilippe Mathieu-Daudé static void aspeed_2700_spi1_class_init(ObjectClass *klass, const void *data)
2108bdb3748dSJamin Lin {
2109bdb3748dSJamin Lin     DeviceClass *dc = DEVICE_CLASS(klass);
2110bdb3748dSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
2111bdb3748dSJamin Lin 
2112bdb3748dSJamin Lin     dc->desc               = "Aspeed 2700 SPI1 Controller";
2113bdb3748dSJamin Lin     asc->r_conf            = R_CONF;
2114bdb3748dSJamin Lin     asc->r_ce_ctrl         = R_CE_CTRL;
2115bdb3748dSJamin Lin     asc->r_ctrl0           = R_CTRL0;
2116bdb3748dSJamin Lin     asc->r_timings         = R_TIMINGS;
2117bdb3748dSJamin Lin     asc->nregs_timings     = 2;
2118bdb3748dSJamin Lin     asc->conf_enable_w0    = CONF_ENABLE_W0;
2119bdb3748dSJamin Lin     asc->cs_num_max        = 2;
2120bdb3748dSJamin Lin     asc->segments          = aspeed_2700_spi1_segments;
2121bdb3748dSJamin Lin     asc->segment_addr_mask = 0xffffffff;
2122bdb3748dSJamin Lin     asc->flash_window_base = 0x200000000;
2123bdb3748dSJamin Lin     asc->flash_window_size = 1 * GiB;
2124bdb3748dSJamin Lin     asc->features          = ASPEED_SMC_FEATURE_DMA |
2125bdb3748dSJamin Lin                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
2126bdb3748dSJamin Lin     asc->dma_flash_mask    = 0x2FFFFFFC;
2127bdb3748dSJamin Lin     asc->dma_dram_mask     = 0xFFFFFFFC;
2128bdb3748dSJamin Lin     asc->dma_start_length  = 1;
2129bdb3748dSJamin Lin     asc->nregs             = ASPEED_SMC_R_MAX;
2130bdb3748dSJamin Lin     asc->segment_to_reg    = aspeed_2700_smc_segment_to_reg;
2131bdb3748dSJamin Lin     asc->reg_to_segment    = aspeed_2700_smc_reg_to_segment;
2132bdb3748dSJamin Lin     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
2133bdb3748dSJamin Lin     asc->reg_ops           = &aspeed_2700_smc_flash_ops;
2134bdb3748dSJamin Lin }
2135bdb3748dSJamin Lin 
2136bdb3748dSJamin Lin static const TypeInfo aspeed_2700_spi1_info = {
2137bdb3748dSJamin Lin         .name =  "aspeed.spi1-ast2700",
2138bdb3748dSJamin Lin         .parent = TYPE_ASPEED_SMC,
2139bdb3748dSJamin Lin         .class_init = aspeed_2700_spi1_class_init,
2140bdb3748dSJamin Lin };
2141bdb3748dSJamin Lin 
2142bdb3748dSJamin Lin static const AspeedSegments aspeed_2700_spi2_segments[] = {
2143bdb3748dSJamin Lin     { 0x0, 128 * MiB }, /* start address is readonly */
2144bdb3748dSJamin Lin     { 0x0, 0 }, /* disabled */
2145bdb3748dSJamin Lin };
2146bdb3748dSJamin Lin 
aspeed_2700_spi2_class_init(ObjectClass * klass,const void * data)214712d1a768SPhilippe Mathieu-Daudé static void aspeed_2700_spi2_class_init(ObjectClass *klass, const void *data)
2148bdb3748dSJamin Lin {
2149bdb3748dSJamin Lin     DeviceClass *dc = DEVICE_CLASS(klass);
2150bdb3748dSJamin Lin     AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
2151bdb3748dSJamin Lin 
2152bdb3748dSJamin Lin     dc->desc               = "Aspeed 2700 SPI2 Controller";
2153bdb3748dSJamin Lin     asc->r_conf            = R_CONF;
2154bdb3748dSJamin Lin     asc->r_ce_ctrl         = R_CE_CTRL;
2155bdb3748dSJamin Lin     asc->r_ctrl0           = R_CTRL0;
2156bdb3748dSJamin Lin     asc->r_timings         = R_TIMINGS;
2157bdb3748dSJamin Lin     asc->nregs_timings     = 2;
2158bdb3748dSJamin Lin     asc->conf_enable_w0    = CONF_ENABLE_W0;
2159bdb3748dSJamin Lin     asc->cs_num_max        = 2;
2160bdb3748dSJamin Lin     asc->segments          = aspeed_2700_spi2_segments;
2161bdb3748dSJamin Lin     asc->segment_addr_mask = 0xffffffff;
2162bdb3748dSJamin Lin     asc->flash_window_base = 0x280000000;
2163bdb3748dSJamin Lin     asc->flash_window_size = 1 * GiB;
2164bdb3748dSJamin Lin     asc->features          = ASPEED_SMC_FEATURE_DMA |
2165bdb3748dSJamin Lin                              ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
2166bdb3748dSJamin Lin     asc->dma_flash_mask    = 0x0FFFFFFC;
2167bdb3748dSJamin Lin     asc->dma_dram_mask     = 0xFFFFFFFC;
2168bdb3748dSJamin Lin     asc->dma_start_length  = 1;
2169bdb3748dSJamin Lin     asc->nregs             = ASPEED_SMC_R_MAX;
2170bdb3748dSJamin Lin     asc->segment_to_reg    = aspeed_2700_smc_segment_to_reg;
2171bdb3748dSJamin Lin     asc->reg_to_segment    = aspeed_2700_smc_reg_to_segment;
2172bdb3748dSJamin Lin     asc->dma_ctrl          = aspeed_2600_smc_dma_ctrl;
2173bdb3748dSJamin Lin     asc->reg_ops           = &aspeed_2700_smc_flash_ops;
2174bdb3748dSJamin Lin }
2175bdb3748dSJamin Lin 
2176bdb3748dSJamin Lin static const TypeInfo aspeed_2700_spi2_info = {
2177bdb3748dSJamin Lin         .name =  "aspeed.spi2-ast2700",
2178bdb3748dSJamin Lin         .parent = TYPE_ASPEED_SMC,
2179bdb3748dSJamin Lin         .class_init = aspeed_2700_spi2_class_init,
2180bdb3748dSJamin Lin };
2181bdb3748dSJamin Lin 
aspeed_smc_register_types(void)21827c1c69bcSCédric Le Goater static void aspeed_smc_register_types(void)
21837c1c69bcSCédric Le Goater {
2184f75b5331SCédric Le Goater     type_register_static(&aspeed_smc_flash_info);
21857c1c69bcSCédric Le Goater     type_register_static(&aspeed_smc_info);
218630b6852cSCédric Le Goater     type_register_static(&aspeed_2400_smc_info);
218730b6852cSCédric Le Goater     type_register_static(&aspeed_2400_fmc_info);
218830b6852cSCédric Le Goater     type_register_static(&aspeed_2400_spi1_info);
218930b6852cSCédric Le Goater     type_register_static(&aspeed_2500_fmc_info);
219030b6852cSCédric Le Goater     type_register_static(&aspeed_2500_spi1_info);
219130b6852cSCédric Le Goater     type_register_static(&aspeed_2500_spi2_info);
219230b6852cSCédric Le Goater     type_register_static(&aspeed_2600_fmc_info);
219330b6852cSCédric Le Goater     type_register_static(&aspeed_2600_spi1_info);
219430b6852cSCédric Le Goater     type_register_static(&aspeed_2600_spi2_info);
21952850df6aSSteven Lee     type_register_static(&aspeed_1030_fmc_info);
21962850df6aSSteven Lee     type_register_static(&aspeed_1030_spi1_info);
21972850df6aSSteven Lee     type_register_static(&aspeed_1030_spi2_info);
2198bdb3748dSJamin Lin     type_register_static(&aspeed_2700_fmc_info);
2199bdb3748dSJamin Lin     type_register_static(&aspeed_2700_spi0_info);
2200bdb3748dSJamin Lin     type_register_static(&aspeed_2700_spi1_info);
2201bdb3748dSJamin Lin     type_register_static(&aspeed_2700_spi2_info);
22027c1c69bcSCédric Le Goater }
22037c1c69bcSCédric Le Goater 
22047c1c69bcSCédric Le Goater type_init(aspeed_smc_register_types)
2205