1*69fbfb8fSHao Wu /* 2*69fbfb8fSHao Wu * Nuvoton Peripheral SPI Module 3*69fbfb8fSHao Wu * 4*69fbfb8fSHao Wu * Copyright 2023 Google LLC 5*69fbfb8fSHao Wu * 6*69fbfb8fSHao Wu * This program is free software; you can redistribute it and/or modify it 7*69fbfb8fSHao Wu * under the terms of the GNU General Public License as published by the 8*69fbfb8fSHao Wu * Free Software Foundation; either version 2 of the License, or 9*69fbfb8fSHao Wu * (at your option) any later version. 10*69fbfb8fSHao Wu * 11*69fbfb8fSHao Wu * This program is distributed in the hope that it will be useful, but WITHOUT 12*69fbfb8fSHao Wu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13*69fbfb8fSHao Wu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14*69fbfb8fSHao Wu * for more details. 15*69fbfb8fSHao Wu */ 16*69fbfb8fSHao Wu #ifndef NPCM_PSPI_H 17*69fbfb8fSHao Wu #define NPCM_PSPI_H 18*69fbfb8fSHao Wu 19*69fbfb8fSHao Wu #include "hw/ssi/ssi.h" 20*69fbfb8fSHao Wu #include "hw/sysbus.h" 21*69fbfb8fSHao Wu 22*69fbfb8fSHao Wu /* 23*69fbfb8fSHao Wu * Number of registers in our device state structure. Don't change this without 24*69fbfb8fSHao Wu * incrementing the version_id in the vmstate. 25*69fbfb8fSHao Wu */ 26*69fbfb8fSHao Wu #define NPCM_PSPI_NR_REGS 3 27*69fbfb8fSHao Wu 28*69fbfb8fSHao Wu /** 29*69fbfb8fSHao Wu * NPCMPSPIState - Device state for one Flash Interface Unit. 30*69fbfb8fSHao Wu * @parent: System bus device. 31*69fbfb8fSHao Wu * @mmio: Memory region for register access. 32*69fbfb8fSHao Wu * @spi: The SPI bus mastered by this controller. 33*69fbfb8fSHao Wu * @regs: Register contents. 34*69fbfb8fSHao Wu * @irq: The interrupt request queue for this module. 35*69fbfb8fSHao Wu * 36*69fbfb8fSHao Wu * Each PSPI has a shared bank of registers, and controls up to four chip 37*69fbfb8fSHao Wu * selects. Each chip select has a dedicated memory region which may be used to 38*69fbfb8fSHao Wu * read and write the flash connected to that chip select as if it were memory. 39*69fbfb8fSHao Wu */ 40*69fbfb8fSHao Wu typedef struct NPCMPSPIState { 41*69fbfb8fSHao Wu SysBusDevice parent; 42*69fbfb8fSHao Wu 43*69fbfb8fSHao Wu MemoryRegion mmio; 44*69fbfb8fSHao Wu 45*69fbfb8fSHao Wu SSIBus *spi; 46*69fbfb8fSHao Wu uint16_t regs[NPCM_PSPI_NR_REGS]; 47*69fbfb8fSHao Wu qemu_irq irq; 48*69fbfb8fSHao Wu } NPCMPSPIState; 49*69fbfb8fSHao Wu 50*69fbfb8fSHao Wu #define TYPE_NPCM_PSPI "npcm-pspi" 51*69fbfb8fSHao Wu OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) 52*69fbfb8fSHao Wu 53*69fbfb8fSHao Wu #endif /* NPCM_PSPI_H */ 54