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/kvm-unit-tests/lib/s390x/
H A Dmmu.h31 * Applies the given protection bits to the given DAT tables level,
34 * @vaddr address whose protection bits are to be changed
35 * @prot the protection bits to set
41 * Clears the given protection bits from the given DAT tables level,
44 * @vaddr address whose protection bits are to be changed
45 * @prot the protection bits to clear
51 * Applies the given protection bits to the given 4kB pages range,
53 * @start starting address whose protection bits are to be changed
55 * @prot the protection bits to set
60 * Clears the given protection bits from the given 4kB pages range,
[all …]
/kvm-unit-tests/lib/x86/asm/
H A Ddebugreg.h8 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits (e.g. RTM), and is also
36 * Enable bits for DR0-D3. Bits 0, 2, 4, and 6 are local enable bits (cleared
37 * by the CPU on task switch), bits 1, 3, 5, and 7 are global enable bits
/kvm-unit-tests/lib/arm64/asm/
H A Dptrace.h18 * PSR bits
29 /* AArch32 CPSR bits */
32 /* AArch64 SPSR bits */
44 * Groups of PSR bits
H A Darch_gicv3.h21 * These system registers are 32 bits, but we make sure that the compiler
22 * sets the GP register's most significant bits to 0 with an explicit cast.
H A Dpage.h32 * Since a page table descriptor is 8 bytes we have (PAGE_SHIFT - 3) bits
35 * address bits (VA_BITS - PAGE_SHIFT) by (PAGE_SHIFT - 3).
/kvm-unit-tests/s390x/
H A Depsw.c58 "upper 32 bits unmodified"); in test_epsw()
61 "lower 32 bits modified"); in test_epsw()
76 "upper 32 bits of first operand unmodified"); in test_epsw()
92 "upper 32 bits of first operand unmodified"); in test_epsw()
H A Dsclp.c218 /* addresses with 1 bit set in the first 33 bits */ in test_sccb_high()
221 /* addresses with 2 consecutive bits set in the first 33 bits */ in test_sccb_high()
224 /* addresses with all bits set in bits 0..N */ in test_sccb_high()
227 /* addresses with all bits set in bits N..33 */ in test_sccb_high()
397 * Test some bits in the instruction format that are specified to be ignored.
425 report(cc == 0, "Instruction format ignored bits"); in test_instbits()
H A Dmigration-skey.c55 * Only the lower seven bits of the seed are considered.
66 * This loop will set all 7 bits which means we set fetch in set_test_pattern()
102 * don't rely on it and just clear the bits to avoid compare in verify_test_pattern()
/kvm-unit-tests/lib/linux/
H A Dpci_regs.h30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
45 #define PCI_STATUS 0x06 /* 16 bits */
62 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
67 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
68 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
69 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
74 #define PCI_BIST 0x0f /* 8 bits */
83 * 1 bits are decoded.
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H A Dcompiler.h83 * the machine (e.g., 32 bits or 64 bits) READ_ONCE() and WRITE_ONCE() will
/kvm-unit-tests/x86/
H A Dunittests.cfg118 qemu_params = -cpu max,host-phys-bits
124 qemu_params = -cpu max,host-phys-bits
131 qemu_params = -cpu IvyBridge,phys-bits=36,host-phys-bits=off
318 qemu_params = -cpu max,host-phys-bits
330 qemu_params = -cpu max,host-phys-bits,+vmx -m 2560
451 qemu_params = -cpu IvyBridge,phys-bits=36,host-phys-bits=off,+vmx
H A Dmsr.c63 * and conversely setting those bits on 32-bit CPUs is not allowed. Treat in __test_msr_rw()
64 * the desired value as extra bits to set. in __test_msr_rw()
196 * The ADDR is a physical address, and all bits are writable on in test_mce_msrs()
198 * enforce checks on bits 63:36 for 32-bit hosts. The behavior in test_mce_msrs()
258 * Except for ICR, the only 64-bit x2APIC register, bits 64:32 in __test_x2apic_msrs()
264 /* Bits 31:8 of self-IPI are reserved. */ in __test_x2apic_msrs()
277 "Expected bits 63:32 == 0 for '%s'", msr_name); in __test_x2apic_msrs()
H A DMakefile.i3862 bits = 32
H A Dlam.c234 * The physical address of AREA_NORMAL is within 36 bits, so that using in test_lam_user()
236 * address from the view of LAM, and the metadata bits are not used as in test_lam_user()
246 * doesn't expose LAM to guest, the guest can still set LAM control bits in test_lam_user()
250 * Only enable LAM CR3 bits when LAM feature is exposed. in test_lam_user()
H A Dxsave.c28 printf("Supported XCR0 bits: %#lx\n", supported_xcr0); in test_xsave()
32 "Check minimal XSAVE required bits"); in test_xsave()
H A Dvmx_tests.c27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that
1037 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries
1079 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries
1099 * accessed/dirty bits at 4K granularity. in setup_ept()
1159 test_skip("EPT AD bits not supported."); in ept_enable_ad_bits_or_skip_test()
1508 printf("\tEPT A/D bits are not supported"); in eptad_init()
2320 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into
2362 /* Mask undefined bits (which may later be defined in certain cases). */ in do_ept_violation()
2447 * @pte_ad Set the A/D bits on the guest PTE accordingly.
2477 * Now modify the access bits on the EPT entry for the GPA that the in ept_access_paddr()
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H A Dsvm_npt.c236 "Wanted #NPF on rsvd bits = 0x%lx, got exit = 0x%x", rsvd_bits, in __svm_npt_rsvd_bits_test()
272 * RDTSC or RDRAND can sometimes fail to generate a valid reserved bits in _svm_npt_rsvd_bits_test()
276 ("svm_npt_rsvd_bits_test: Reserved bits are not valid"); in _svm_npt_rsvd_bits_test()
352 * 4k PTEs don't have reserved bits if MAXPHYADDR >= 52, just skip the in svm_npt_rsvd_bits_test()
H A Dintel-iommu.c101 /* Clear INTR bits */ in vtd_test_ir()
148 "DMAR support 39 bits address width"); in main()
/kvm-unit-tests/lib/s390x/asm/
H A Darch_def.h384 * psw_mask_clear_bits - clears bits from the current PSW mask
385 * @clear: bitmask of bits that will be cleared
393 * psw_mask_set_bits - sets bits on the current PSW mask
394 * @set: bitmask of bits that will be set
402 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask
403 * @clear: bitmask of bits that will be cleared
404 * @set: bitmask of bits that will be set
406 * The bits in the @clear mask will be cleared, then the bits in the @set mask
H A Dcmm.h40 * Unfortunately the availability is not indicated by stfl bits, but
/kvm-unit-tests/lib/arm/asm/
H A Dptrace.h14 * PSR bits
40 * Groups of PSR bits
48 * ARMv7 groups of PSR bits
/kvm-unit-tests/lib/x86/
H A Dmsr.h17 /* EFER bits: */
99 /* DEBUGCTLMSR bits (others vary by model): */
232 /* C1E active bits in int pending message */
352 /* MISC_ENABLE bits: architectural */
364 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
517 /* MSR_IA32_VMX_MISC bits */
/kvm-unit-tests/powerpc/
H A DMakefile.ppc646 bits = 64
H A Dspapr_hcall.c102 * positions really toggle (there should be no "stuck" bits in the output)
132 report(rc == H_SUCCESS && val0 == ~0ULL && val1 == 0, "no stuck bits"); in test_h_random()
/kvm-unit-tests/arm/
H A DMakefile.arm6 bits = 32

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