16c9f99dfSJanosch Frank /* SPDX-License-Identifier: GPL-2.0-only */
2cfb204f9SDavid Hildenbrand /*
3cfb204f9SDavid Hildenbrand * Copyright (c) 2017 Red Hat Inc
4cfb204f9SDavid Hildenbrand *
5cfb204f9SDavid Hildenbrand * Authors:
6cfb204f9SDavid Hildenbrand * David Hildenbrand <david@redhat.com>
7cfb204f9SDavid Hildenbrand */
8eb5a1bbaSCornelia Huck #ifndef _ASMS390X_ARCH_DEF_H_
9eb5a1bbaSCornelia Huck #define _ASMS390X_ARCH_DEF_H_
10cfb204f9SDavid Hildenbrand
113ae7f80fSJanosch Frank struct stack_frame {
1236cfc0b7SJanosch Frank struct stack_frame *back_chain;
1336cfc0b7SJanosch Frank uint64_t reserved;
1436cfc0b7SJanosch Frank /* GRs 2 - 5 */
1536cfc0b7SJanosch Frank uint64_t argument_area[4];
1636cfc0b7SJanosch Frank /* GRs 6 - 15 */
1736cfc0b7SJanosch Frank uint64_t grs[10];
1836cfc0b7SJanosch Frank /* FPRs 0, 2, 4, 6 */
1936cfc0b7SJanosch Frank int64_t fprs[4];
2036cfc0b7SJanosch Frank };
2136cfc0b7SJanosch Frank
2236cfc0b7SJanosch Frank struct stack_frame_int {
2336cfc0b7SJanosch Frank struct stack_frame *back_chain;
2436cfc0b7SJanosch Frank uint64_t reserved;
2536cfc0b7SJanosch Frank /*
2636cfc0b7SJanosch Frank * The GRs are offset compatible with struct stack_frame so we
2736cfc0b7SJanosch Frank * can easily fetch GR14 for backtraces.
2836cfc0b7SJanosch Frank */
2936cfc0b7SJanosch Frank /* GRs 2 - 15 */
3036cfc0b7SJanosch Frank uint64_t grs0[14];
3136cfc0b7SJanosch Frank /* GRs 0 and 1 */
3236cfc0b7SJanosch Frank uint64_t grs1[2];
3336cfc0b7SJanosch Frank uint32_t reserved1;
3436cfc0b7SJanosch Frank uint32_t fpc;
3536cfc0b7SJanosch Frank uint64_t fprs[16];
3636cfc0b7SJanosch Frank uint64_t crs[16];
373ae7f80fSJanosch Frank };
383ae7f80fSJanosch Frank
39cfb204f9SDavid Hildenbrand struct psw {
40f0721060SNico Boehr union {
41cfb204f9SDavid Hildenbrand uint64_t mask;
42f0721060SNico Boehr struct {
43f0721060SNico Boehr uint64_t reserved00:1;
44f0721060SNico Boehr uint64_t per:1;
45f0721060SNico Boehr uint64_t reserved02:3;
46f0721060SNico Boehr uint64_t dat:1;
47f0721060SNico Boehr uint64_t io:1;
48f0721060SNico Boehr uint64_t ext:1;
49f0721060SNico Boehr uint64_t key:4;
50f0721060SNico Boehr uint64_t reserved12:1;
51f0721060SNico Boehr uint64_t mchk:1;
52f0721060SNico Boehr uint64_t wait:1;
53f0721060SNico Boehr uint64_t pstate:1;
54f0721060SNico Boehr uint64_t as:2;
55f0721060SNico Boehr uint64_t cc:2;
56f0721060SNico Boehr uint64_t prg_mask:4;
57f0721060SNico Boehr uint64_t reserved24:7;
58f0721060SNico Boehr uint64_t ea:1;
59f0721060SNico Boehr uint64_t ba:1;
60f0721060SNico Boehr uint64_t reserved33:31;
61f0721060SNico Boehr };
62f0721060SNico Boehr };
63cfb204f9SDavid Hildenbrand uint64_t addr;
64cfb204f9SDavid Hildenbrand };
65f0721060SNico Boehr _Static_assert(sizeof(struct psw) == 16, "PSW size");
66cfb204f9SDavid Hildenbrand
6703dca0b5SClaudio Imbrenda #define PSW(m, a) ((struct psw){ .mask = (m), .addr = (uint64_t)(a) })
6803dca0b5SClaudio Imbrenda
69e08c4f5eSJanis Schoetterl-Glausch struct short_psw {
70e08c4f5eSJanis Schoetterl-Glausch uint32_t mask;
71e08c4f5eSJanis Schoetterl-Glausch uint32_t addr;
72e08c4f5eSJanis Schoetterl-Glausch };
73e08c4f5eSJanis Schoetterl-Glausch
744e5dd758SClaudio Imbrenda struct cpu {
754e5dd758SClaudio Imbrenda struct lowcore *lowcore;
764e5dd758SClaudio Imbrenda uint64_t *stack;
774e5dd758SClaudio Imbrenda void (*pgm_cleanup_func)(struct stack_frame_int *);
784e5dd758SClaudio Imbrenda void (*ext_cleanup_func)(struct stack_frame_int *);
794e5dd758SClaudio Imbrenda uint16_t addr;
804e5dd758SClaudio Imbrenda uint16_t idx;
814e5dd758SClaudio Imbrenda bool active;
824e5dd758SClaudio Imbrenda bool pgm_int_expected;
834e5dd758SClaudio Imbrenda bool ext_int_expected;
8489ce5095SClaudio Imbrenda bool in_interrupt_handler;
854e5dd758SClaudio Imbrenda };
864e5dd758SClaudio Imbrenda
87fedfd112SNico Boehr enum address_space {
88fedfd112SNico Boehr AS_PRIM = 0,
89fedfd112SNico Boehr AS_ACCR = 1,
90fedfd112SNico Boehr AS_SECN = 2,
91fedfd112SNico Boehr AS_HOME = 3
92fedfd112SNico Boehr };
931921c4c6SJanosch Frank
94c08c320bSDavid Hildenbrand #define PSW_MASK_DAT 0x0400000000000000UL
954e8880d6SNico Boehr #define PSW_MASK_HOME 0x0000C00000000000UL
96086985a3SClaudio Imbrenda #define PSW_MASK_IO 0x0200000000000000UL
97086985a3SClaudio Imbrenda #define PSW_MASK_EXT 0x0100000000000000UL
98086985a3SClaudio Imbrenda #define PSW_MASK_KEY 0x00F0000000000000UL
99f73b4b9eSPierre Morel #define PSW_MASK_WAIT 0x0002000000000000UL
1004ef6f57dSJanosch Frank #define PSW_MASK_PSTATE 0x0001000000000000UL
10144026818SJanosch Frank #define PSW_MASK_EA 0x0000000100000000UL
10244026818SJanosch Frank #define PSW_MASK_BA 0x0000000080000000UL
1034f26290bSJanosch Frank #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA)
104c08c320bSDavid Hildenbrand
105fb955075SJanis Schoetterl-Glausch #define CTL0_TRANSACT_EX_CTL (63 - 8)
106d34d3250SJanosch Frank #define CTL0_LOW_ADDR_PROT (63 - 35)
107d34d3250SJanosch Frank #define CTL0_EDAT (63 - 40)
10866abce92SJanis Schoetterl-Glausch #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38)
10966abce92SJanis Schoetterl-Glausch #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39)
110d34d3250SJanosch Frank #define CTL0_IEP (63 - 43)
111d34d3250SJanosch Frank #define CTL0_AFP (63 - 45)
112d34d3250SJanosch Frank #define CTL0_VECTOR (63 - 46)
113d34d3250SJanosch Frank #define CTL0_EMERGENCY_SIGNAL (63 - 49)
114d34d3250SJanosch Frank #define CTL0_EXTERNAL_CALL (63 - 50)
115d34d3250SJanosch Frank #define CTL0_CLOCK_COMPARATOR (63 - 52)
11608a584f7SNico Boehr #define CTL0_CPU_TIMER (63 - 53)
117d34d3250SJanosch Frank #define CTL0_SERVICE_SIGNAL (63 - 54)
118d34d3250SJanosch Frank #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */
119d34d3250SJanosch Frank
120d34d3250SJanosch Frank #define CTL2_GUARDED_STORAGE (63 - 59)
121df121a0cSJanosch Frank
122638bbf66SNico Boehr #define LC_SIZE (2 * PAGE_SIZE)
123cfb204f9SDavid Hildenbrand struct lowcore {
124cfb204f9SDavid Hildenbrand uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */
125cfb204f9SDavid Hildenbrand uint32_t ext_int_param; /* 0x0080 */
126cfb204f9SDavid Hildenbrand uint16_t cpu_addr; /* 0x0084 */
127cfb204f9SDavid Hildenbrand uint16_t ext_int_code; /* 0x0086 */
128cfb204f9SDavid Hildenbrand uint16_t svc_int_id; /* 0x0088 */
129cfb204f9SDavid Hildenbrand uint16_t svc_int_code; /* 0x008a */
130cfb204f9SDavid Hildenbrand uint16_t pgm_int_id; /* 0x008c */
131cfb204f9SDavid Hildenbrand uint16_t pgm_int_code; /* 0x008e */
132cfb204f9SDavid Hildenbrand uint32_t dxc_vxc; /* 0x0090 */
133cfb204f9SDavid Hildenbrand uint16_t mon_class_nb; /* 0x0094 */
134cfb204f9SDavid Hildenbrand uint8_t per_code; /* 0x0096 */
135cfb204f9SDavid Hildenbrand uint8_t per_atmid; /* 0x0097 */
136cfb204f9SDavid Hildenbrand uint64_t per_addr; /* 0x0098 */
137cfb204f9SDavid Hildenbrand uint8_t exc_acc_id; /* 0x00a0 */
138cfb204f9SDavid Hildenbrand uint8_t per_acc_id; /* 0x00a1 */
139cfb204f9SDavid Hildenbrand uint8_t op_acc_id; /* 0x00a2 */
140cfb204f9SDavid Hildenbrand uint8_t arch_mode_id; /* 0x00a3 */
141cfb204f9SDavid Hildenbrand uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */
142cfb204f9SDavid Hildenbrand uint64_t trans_exc_id; /* 0x00a8 */
143cfb204f9SDavid Hildenbrand uint64_t mon_code; /* 0x00b0 */
144cfb204f9SDavid Hildenbrand uint32_t subsys_id_word; /* 0x00b8 */
145cfb204f9SDavid Hildenbrand uint32_t io_int_param; /* 0x00bc */
146cfb204f9SDavid Hildenbrand uint32_t io_int_word; /* 0x00c0 */
147cfb204f9SDavid Hildenbrand uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */
148cfb204f9SDavid Hildenbrand uint32_t stfl; /* 0x00c8 */
149cfb204f9SDavid Hildenbrand uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */
150cfb204f9SDavid Hildenbrand uint64_t mcck_int_code; /* 0x00e8 */
151cfb204f9SDavid Hildenbrand uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */
152cfb204f9SDavid Hildenbrand uint32_t ext_damage_code; /* 0x00f4 */
153cfb204f9SDavid Hildenbrand uint64_t failing_storage_addr; /* 0x00f8 */
154cfb204f9SDavid Hildenbrand uint64_t emon_ca_origin; /* 0x0100 */
155cfb204f9SDavid Hildenbrand uint32_t emon_ca_size; /* 0x0108 */
156cfb204f9SDavid Hildenbrand uint32_t emon_exc_count; /* 0x010c */
157cfb204f9SDavid Hildenbrand uint64_t breaking_event_addr; /* 0x0110 */
158cfb204f9SDavid Hildenbrand uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */
159cfb204f9SDavid Hildenbrand struct psw restart_old_psw; /* 0x0120 */
160cfb204f9SDavid Hildenbrand struct psw ext_old_psw; /* 0x0130 */
161cfb204f9SDavid Hildenbrand struct psw svc_old_psw; /* 0x0140 */
162cfb204f9SDavid Hildenbrand struct psw pgm_old_psw; /* 0x0150 */
163cfb204f9SDavid Hildenbrand struct psw mcck_old_psw; /* 0x0160 */
164cfb204f9SDavid Hildenbrand struct psw io_old_psw; /* 0x0170 */
165cfb204f9SDavid Hildenbrand uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */
166cfb204f9SDavid Hildenbrand struct psw restart_new_psw; /* 0x01a0 */
167cfb204f9SDavid Hildenbrand struct psw ext_new_psw; /* 0x01b0 */
168cfb204f9SDavid Hildenbrand struct psw svc_new_psw; /* 0x01c0 */
169cfb204f9SDavid Hildenbrand struct psw pgm_new_psw; /* 0x01d0 */
170cfb204f9SDavid Hildenbrand struct psw mcck_new_psw; /* 0x01e0 */
171cfb204f9SDavid Hildenbrand struct psw io_new_psw; /* 0x01f0 */
1724da93626SDavid Hildenbrand /* sw definition: save area for registers in interrupt handlers */
1734da93626SDavid Hildenbrand uint64_t sw_int_grs[16]; /* 0x0200 */
1743a92a013SJanosch Frank uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */
175736b9295SJanosch Frank uint64_t sw_int_crs[16]; /* 0x0308 */
176da6ce270SJanosch Frank struct psw sw_int_psw; /* 0x0388 */
1774e5dd758SClaudio Imbrenda struct cpu *this_cpu; /* 0x0398 */
1784e5dd758SClaudio Imbrenda uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */
179cfb204f9SDavid Hildenbrand uint64_t mcck_ext_sa_addr; /* 0x11b0 */
180cfb204f9SDavid Hildenbrand uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */
181cfb204f9SDavid Hildenbrand uint64_t fprs_sa[16]; /* 0x1200 */
182cfb204f9SDavid Hildenbrand uint64_t grs_sa[16]; /* 0x1280 */
183cfb204f9SDavid Hildenbrand struct psw psw_sa; /* 0x1300 */
184cfb204f9SDavid Hildenbrand uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */
185cfb204f9SDavid Hildenbrand uint32_t prefix_sa; /* 0x1318 */
186cfb204f9SDavid Hildenbrand uint32_t fpc_sa; /* 0x131c */
187cfb204f9SDavid Hildenbrand uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */
188cfb204f9SDavid Hildenbrand uint32_t tod_pr_sa; /* 0x1324 */
189cfb204f9SDavid Hildenbrand uint64_t cputm_sa; /* 0x1328 */
190cfb204f9SDavid Hildenbrand uint64_t cc_sa; /* 0x1330 */
191cfb204f9SDavid Hildenbrand uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */
192cfb204f9SDavid Hildenbrand uint32_t ars_sa[16]; /* 0x1340 */
193cfb204f9SDavid Hildenbrand uint64_t crs_sa[16]; /* 0x1380 */
194cfb204f9SDavid Hildenbrand uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */
195cfb204f9SDavid Hildenbrand uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */
196cfb204f9SDavid Hildenbrand } __attribute__ ((__packed__));
197da6ce270SJanosch Frank _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size");
198cfb204f9SDavid Hildenbrand
199cd719531SJanis Schoetterl-Glausch extern struct lowcore lowcore;
200cd719531SJanis Schoetterl-Glausch
2014e5dd758SClaudio Imbrenda #define THIS_CPU (lowcore.this_cpu)
2024e5dd758SClaudio Imbrenda
2034da93626SDavid Hildenbrand #define PGM_INT_CODE_OPERATION 0x01
2044da93626SDavid Hildenbrand #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02
2054da93626SDavid Hildenbrand #define PGM_INT_CODE_EXECUTE 0x03
2064da93626SDavid Hildenbrand #define PGM_INT_CODE_PROTECTION 0x04
2074da93626SDavid Hildenbrand #define PGM_INT_CODE_ADDRESSING 0x05
2084da93626SDavid Hildenbrand #define PGM_INT_CODE_SPECIFICATION 0x06
2094da93626SDavid Hildenbrand #define PGM_INT_CODE_DATA 0x07
2104da93626SDavid Hildenbrand #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08
2114da93626SDavid Hildenbrand #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09
2124da93626SDavid Hildenbrand #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a
2134da93626SDavid Hildenbrand #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b
2144da93626SDavid Hildenbrand #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c
2154da93626SDavid Hildenbrand #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d
2164da93626SDavid Hildenbrand #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e
2174da93626SDavid Hildenbrand #define PGM_INT_CODE_HFP_DIVIDE 0x0f
2184da93626SDavid Hildenbrand #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10
2194da93626SDavid Hildenbrand #define PGM_INT_CODE_PAGE_TRANSLATION 0x11
2204da93626SDavid Hildenbrand #define PGM_INT_CODE_TRANSLATION_SPEC 0x12
2214da93626SDavid Hildenbrand #define PGM_INT_CODE_SPECIAL_OPERATION 0x13
2224da93626SDavid Hildenbrand #define PGM_INT_CODE_OPERAND 0x15
2234da93626SDavid Hildenbrand #define PGM_INT_CODE_TRACE_TABLE 0x16
2244da93626SDavid Hildenbrand #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b
2254da93626SDavid Hildenbrand #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c
2264da93626SDavid Hildenbrand #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d
2274da93626SDavid Hildenbrand #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f
2284da93626SDavid Hildenbrand #define PGM_INT_CODE_AFX_TRANSLATION 0x20
2294da93626SDavid Hildenbrand #define PGM_INT_CODE_ASX_TRANSLATION 0x21
2304da93626SDavid Hildenbrand #define PGM_INT_CODE_LX_TRANSLATION 0x22
2314da93626SDavid Hildenbrand #define PGM_INT_CODE_EX_TRANSLATION 0x23
2324da93626SDavid Hildenbrand #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24
2334da93626SDavid Hildenbrand #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25
2344da93626SDavid Hildenbrand #define PGM_INT_CODE_LFX_TRANSLATION 0x26
2354da93626SDavid Hildenbrand #define PGM_INT_CODE_LSX_TRANSLATION 0x27
2364da93626SDavid Hildenbrand #define PGM_INT_CODE_ALET_SPECIFICATION 0x28
2374da93626SDavid Hildenbrand #define PGM_INT_CODE_ALEN_TRANSLATION 0x29
2384da93626SDavid Hildenbrand #define PGM_INT_CODE_ALE_SEQUENCE 0x2a
2394da93626SDavid Hildenbrand #define PGM_INT_CODE_ASTE_VALIDITY 0x2b
2404da93626SDavid Hildenbrand #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c
2414da93626SDavid Hildenbrand #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d
2424da93626SDavid Hildenbrand #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e
2434da93626SDavid Hildenbrand #define PGM_INT_CODE_ASTE_INSTANCE 0x2f
2444da93626SDavid Hildenbrand #define PGM_INT_CODE_STACK_FULL 0x30
2454da93626SDavid Hildenbrand #define PGM_INT_CODE_STACK_EMPTY 0x31
2464da93626SDavid Hildenbrand #define PGM_INT_CODE_STACK_SPECIFICATION 0x32
2474da93626SDavid Hildenbrand #define PGM_INT_CODE_STACK_TYPE 0x33
2484da93626SDavid Hildenbrand #define PGM_INT_CODE_STACK_OPERATION 0x34
2494da93626SDavid Hildenbrand #define PGM_INT_CODE_ASCE_TYPE 0x38
2504da93626SDavid Hildenbrand #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39
2514da93626SDavid Hildenbrand #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a
2524da93626SDavid Hildenbrand #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b
25368721b97SJanosch Frank #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d
25468721b97SJanosch Frank #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e
25568721b97SJanosch Frank #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f
2564da93626SDavid Hildenbrand #define PGM_INT_CODE_MONITOR_EVENT 0x40
2574da93626SDavid Hildenbrand #define PGM_INT_CODE_PER 0x80
2584da93626SDavid Hildenbrand #define PGM_INT_CODE_CRYPTO_OPERATION 0x119
2594da93626SDavid Hildenbrand #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200
2604da93626SDavid Hildenbrand
261484a3a57SDavid Hildenbrand struct cpuid {
262484a3a57SDavid Hildenbrand uint64_t version : 8;
263484a3a57SDavid Hildenbrand uint64_t id : 24;
264484a3a57SDavid Hildenbrand uint64_t type : 16;
265484a3a57SDavid Hildenbrand uint64_t format : 1;
266484a3a57SDavid Hildenbrand uint64_t reserved : 15;
267484a3a57SDavid Hildenbrand };
268484a3a57SDavid Hildenbrand
269b43c912fSClaudio Imbrenda #define SVC_LEAVE_PSTATE 1
270b43c912fSClaudio Imbrenda
stap(void)271f77c0515SJanosch Frank static inline unsigned short stap(void)
272f77c0515SJanosch Frank {
273f77c0515SJanosch Frank unsigned short cpu_address;
274f77c0515SJanosch Frank
275f77c0515SJanosch Frank asm volatile("stap %0" : "=Q" (cpu_address));
276f77c0515SJanosch Frank return cpu_address;
277f77c0515SJanosch Frank }
278f77c0515SJanosch Frank
stidp(void)27995da193aSClaudio Imbrenda static inline uint64_t stidp(void)
280c73cc92dSJanosch Frank {
281c73cc92dSJanosch Frank uint64_t cpuid;
282c73cc92dSJanosch Frank
283c73cc92dSJanosch Frank asm volatile("stidp %0" : "=Q" (cpuid));
284c73cc92dSJanosch Frank
285c73cc92dSJanosch Frank return cpuid;
286c73cc92dSJanosch Frank }
287c73cc92dSJanosch Frank
288b5b28387SJanis Schoetterl-Glausch enum tprot_permission {
289b5b28387SJanis Schoetterl-Glausch TPROT_READ_WRITE = 0,
290b5b28387SJanis Schoetterl-Glausch TPROT_READ = 1,
291b5b28387SJanis Schoetterl-Glausch TPROT_RW_PROTECTED = 2,
292b5b28387SJanis Schoetterl-Glausch TPROT_TRANSL_UNAVAIL = 3,
293b5b28387SJanis Schoetterl-Glausch };
294b5b28387SJanis Schoetterl-Glausch
tprot(unsigned long addr,char access_key)295b5b28387SJanis Schoetterl-Glausch static inline enum tprot_permission tprot(unsigned long addr, char access_key)
2963db880b6SDavid Hildenbrand {
2973db880b6SDavid Hildenbrand int cc;
2983db880b6SDavid Hildenbrand
2993db880b6SDavid Hildenbrand asm volatile(
300443987a6SJanis Schoetterl-Glausch " tprot 0(%1),0(%2)\n"
3013db880b6SDavid Hildenbrand " ipm %0\n"
3023db880b6SDavid Hildenbrand " srl %0,28\n"
303443987a6SJanis Schoetterl-Glausch : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc");
304b5b28387SJanis Schoetterl-Glausch return (enum tprot_permission)cc;
3053db880b6SDavid Hildenbrand }
3063db880b6SDavid Hildenbrand
lctlg(int cr,uint64_t value)307c08c320bSDavid Hildenbrand static inline void lctlg(int cr, uint64_t value)
308c08c320bSDavid Hildenbrand {
309c08c320bSDavid Hildenbrand asm volatile(
310c08c320bSDavid Hildenbrand " lctlg %1,%1,%0\n"
311c08c320bSDavid Hildenbrand : : "Q" (value), "i" (cr));
312c08c320bSDavid Hildenbrand }
313c08c320bSDavid Hildenbrand
stctg(int cr)314c08c320bSDavid Hildenbrand static inline uint64_t stctg(int cr)
315c08c320bSDavid Hildenbrand {
316c08c320bSDavid Hildenbrand uint64_t value;
317c08c320bSDavid Hildenbrand
318c08c320bSDavid Hildenbrand asm volatile(
319c08c320bSDavid Hildenbrand " stctg %1,%1,%0\n"
320c08c320bSDavid Hildenbrand : "=Q" (value) : "i" (cr) : "memory");
321c08c320bSDavid Hildenbrand return value;
322c08c320bSDavid Hildenbrand }
323c08c320bSDavid Hildenbrand
ctl_set_bit(int cr,unsigned int bit)32443868475SJanosch Frank static inline void ctl_set_bit(int cr, unsigned int bit)
32543868475SJanosch Frank {
32643868475SJanosch Frank uint64_t reg;
32743868475SJanosch Frank
32843868475SJanosch Frank reg = stctg(cr);
32943868475SJanosch Frank reg |= 1UL << bit;
33043868475SJanosch Frank lctlg(cr, reg);
33143868475SJanosch Frank }
33243868475SJanosch Frank
ctl_clear_bit(int cr,unsigned int bit)33343868475SJanosch Frank static inline void ctl_clear_bit(int cr, unsigned int bit)
33443868475SJanosch Frank {
33543868475SJanosch Frank uint64_t reg;
33643868475SJanosch Frank
33743868475SJanosch Frank reg = stctg(cr);
33843868475SJanosch Frank reg &= ~(1UL << bit);
33943868475SJanosch Frank lctlg(cr, reg);
34043868475SJanosch Frank }
34143868475SJanosch Frank
extract_psw_mask(void)342c08c320bSDavid Hildenbrand static inline uint64_t extract_psw_mask(void)
343c08c320bSDavid Hildenbrand {
344c08c320bSDavid Hildenbrand uint32_t mask_upper = 0, mask_lower = 0;
345c08c320bSDavid Hildenbrand
346c08c320bSDavid Hildenbrand asm volatile(
347c08c320bSDavid Hildenbrand " epsw %0,%1\n"
34821675e2dSThomas Huth : "=r" (mask_upper), "=a" (mask_lower));
349c08c320bSDavid Hildenbrand
350c08c320bSDavid Hildenbrand return (uint64_t) mask_upper << 32 | mask_lower;
351c08c320bSDavid Hildenbrand }
352c08c320bSDavid Hildenbrand
35303dca0b5SClaudio Imbrenda #define PSW_WITH_CUR_MASK(addr) PSW(extract_psw_mask(), (addr))
35403dca0b5SClaudio Imbrenda
load_psw_mask(uint64_t mask)355c08c320bSDavid Hildenbrand static inline void load_psw_mask(uint64_t mask)
356c08c320bSDavid Hildenbrand {
357c08c320bSDavid Hildenbrand struct psw psw = {
358c08c320bSDavid Hildenbrand .mask = mask,
359c08c320bSDavid Hildenbrand .addr = 0,
360c08c320bSDavid Hildenbrand };
361c08c320bSDavid Hildenbrand uint64_t tmp = 0;
362c08c320bSDavid Hildenbrand
363c08c320bSDavid Hildenbrand asm volatile(
364c08c320bSDavid Hildenbrand " larl %0,0f\n"
365c08c320bSDavid Hildenbrand " stg %0,8(%1)\n"
366c08c320bSDavid Hildenbrand " lpswe 0(%1)\n"
367c08c320bSDavid Hildenbrand "0:\n"
368c08c320bSDavid Hildenbrand : "+r" (tmp) : "a" (&psw) : "memory", "cc" );
369c08c320bSDavid Hildenbrand }
370c08c320bSDavid Hildenbrand
disabled_wait(uint64_t message)37189ce5095SClaudio Imbrenda static inline void disabled_wait(uint64_t message)
37289ce5095SClaudio Imbrenda {
37389ce5095SClaudio Imbrenda struct psw psw = {
37489ce5095SClaudio Imbrenda .mask = PSW_MASK_WAIT, /* Disabled wait */
37589ce5095SClaudio Imbrenda .addr = message,
37689ce5095SClaudio Imbrenda };
37789ce5095SClaudio Imbrenda
37889ce5095SClaudio Imbrenda asm volatile(" lpswe 0(%0)\n" : : "a" (&psw) : "memory", "cc");
37989ce5095SClaudio Imbrenda }
38089ce5095SClaudio Imbrenda
381086985a3SClaudio Imbrenda /**
382086985a3SClaudio Imbrenda * psw_mask_clear_bits - clears bits from the current PSW mask
383086985a3SClaudio Imbrenda * @clear: bitmask of bits that will be cleared
384086985a3SClaudio Imbrenda */
psw_mask_clear_bits(uint64_t clear)385086985a3SClaudio Imbrenda static inline void psw_mask_clear_bits(uint64_t clear)
386086985a3SClaudio Imbrenda {
387086985a3SClaudio Imbrenda load_psw_mask(extract_psw_mask() & ~clear);
388086985a3SClaudio Imbrenda }
389086985a3SClaudio Imbrenda
390086985a3SClaudio Imbrenda /**
391086985a3SClaudio Imbrenda * psw_mask_set_bits - sets bits on the current PSW mask
392086985a3SClaudio Imbrenda * @set: bitmask of bits that will be set
393086985a3SClaudio Imbrenda */
psw_mask_set_bits(uint64_t set)394086985a3SClaudio Imbrenda static inline void psw_mask_set_bits(uint64_t set)
395086985a3SClaudio Imbrenda {
396086985a3SClaudio Imbrenda load_psw_mask(extract_psw_mask() | set);
397086985a3SClaudio Imbrenda }
398086985a3SClaudio Imbrenda
399086985a3SClaudio Imbrenda /**
400086985a3SClaudio Imbrenda * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask
401086985a3SClaudio Imbrenda * @clear: bitmask of bits that will be cleared
402086985a3SClaudio Imbrenda * @set: bitmask of bits that will be set
403086985a3SClaudio Imbrenda *
404086985a3SClaudio Imbrenda * The bits in the @clear mask will be cleared, then the bits in the @set mask
405086985a3SClaudio Imbrenda * will be set.
406086985a3SClaudio Imbrenda */
psw_mask_clear_and_set_bits(uint64_t clear,uint64_t set)407086985a3SClaudio Imbrenda static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set)
408086985a3SClaudio Imbrenda {
409086985a3SClaudio Imbrenda load_psw_mask((extract_psw_mask() & ~clear) | set);
410086985a3SClaudio Imbrenda }
411086985a3SClaudio Imbrenda
412086985a3SClaudio Imbrenda /**
413086985a3SClaudio Imbrenda * enable_dat - enable the DAT bit in the current PSW
414086985a3SClaudio Imbrenda */
enable_dat(void)415086985a3SClaudio Imbrenda static inline void enable_dat(void)
416086985a3SClaudio Imbrenda {
417086985a3SClaudio Imbrenda psw_mask_set_bits(PSW_MASK_DAT);
418086985a3SClaudio Imbrenda }
419086985a3SClaudio Imbrenda
420086985a3SClaudio Imbrenda /**
421086985a3SClaudio Imbrenda * disable_dat - disable the DAT bit in the current PSW
422086985a3SClaudio Imbrenda */
disable_dat(void)423086985a3SClaudio Imbrenda static inline void disable_dat(void)
424086985a3SClaudio Imbrenda {
425086985a3SClaudio Imbrenda psw_mask_clear_bits(PSW_MASK_DAT);
426086985a3SClaudio Imbrenda }
427086985a3SClaudio Imbrenda
wait_for_interrupt(uint64_t irq_mask)428f73b4b9eSPierre Morel static inline void wait_for_interrupt(uint64_t irq_mask)
429f73b4b9eSPierre Morel {
430f73b4b9eSPierre Morel uint64_t psw_mask = extract_psw_mask();
431f73b4b9eSPierre Morel
432f73b4b9eSPierre Morel load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT);
433f73b4b9eSPierre Morel /*
434f73b4b9eSPierre Morel * After being woken and having processed the interrupt, let's restore
435f73b4b9eSPierre Morel * the PSW mask.
436f73b4b9eSPierre Morel */
437f73b4b9eSPierre Morel load_psw_mask(psw_mask);
438f73b4b9eSPierre Morel }
439f73b4b9eSPierre Morel
enter_pstate(void)4404ef6f57dSJanosch Frank static inline void enter_pstate(void)
4414ef6f57dSJanosch Frank {
442086985a3SClaudio Imbrenda psw_mask_set_bits(PSW_MASK_PSTATE);
4434ef6f57dSJanosch Frank }
4444ef6f57dSJanosch Frank
leave_pstate(void)445b43c912fSClaudio Imbrenda static inline void leave_pstate(void)
446b43c912fSClaudio Imbrenda {
447b43c912fSClaudio Imbrenda asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE));
448b43c912fSClaudio Imbrenda }
449b43c912fSClaudio Imbrenda
stsi(void * addr,int fc,int sel1,int sel2)450c132c9e2SJanosch Frank static inline int stsi(void *addr, int fc, int sel1, int sel2)
451c132c9e2SJanosch Frank {
452c132c9e2SJanosch Frank register int r0 asm("0") = (fc << 28) | sel1;
453c132c9e2SJanosch Frank register int r1 asm("1") = sel2;
454c132c9e2SJanosch Frank int cc;
455c132c9e2SJanosch Frank
456c132c9e2SJanosch Frank asm volatile(
457c132c9e2SJanosch Frank "stsi 0(%3)\n"
458c132c9e2SJanosch Frank "ipm %[cc]\n"
459c132c9e2SJanosch Frank "srl %[cc],28\n"
460c132c9e2SJanosch Frank : "+d" (r0), [cc] "=d" (cc)
461c132c9e2SJanosch Frank : "d" (r1), "a" (addr)
462c132c9e2SJanosch Frank : "cc", "memory");
463c132c9e2SJanosch Frank return cc;
464c132c9e2SJanosch Frank }
465c132c9e2SJanosch Frank
stsi_get_fc(void)466242b02e3SPierre Morel static inline unsigned long stsi_get_fc(void)
467242b02e3SPierre Morel {
468242b02e3SPierre Morel register unsigned long r0 asm("0") = 0;
469242b02e3SPierre Morel register unsigned long r1 asm("1") = 0;
470242b02e3SPierre Morel int cc;
471242b02e3SPierre Morel
472242b02e3SPierre Morel asm volatile("stsi 0\n"
473242b02e3SPierre Morel "ipm %[cc]\n"
474242b02e3SPierre Morel "srl %[cc],28\n"
475242b02e3SPierre Morel : "+d" (r0), [cc] "=d" (cc)
476242b02e3SPierre Morel : "d" (r1)
477242b02e3SPierre Morel : "cc", "memory");
478242b02e3SPierre Morel assert(!cc);
479242b02e3SPierre Morel return r0 >> 28;
480242b02e3SPierre Morel }
481242b02e3SPierre Morel
servc(uint32_t command,unsigned long sccb)482f9395bfeSClaudio Imbrenda static inline int servc(uint32_t command, unsigned long sccb)
483f9395bfeSClaudio Imbrenda {
484f9395bfeSClaudio Imbrenda int cc;
485f9395bfeSClaudio Imbrenda
486f9395bfeSClaudio Imbrenda asm volatile(
487f9395bfeSClaudio Imbrenda " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */
488f9395bfeSClaudio Imbrenda " ipm %0\n"
489f9395bfeSClaudio Imbrenda " srl %0,28"
490f9395bfeSClaudio Imbrenda : "=&d" (cc) : "d" (command), "a" (sccb)
491f9395bfeSClaudio Imbrenda : "cc", "memory");
492f9395bfeSClaudio Imbrenda return cc;
493f9395bfeSClaudio Imbrenda }
494f9395bfeSClaudio Imbrenda
set_prefix(uint32_t new_prefix)4956b3278c9SClaudio Imbrenda static inline void set_prefix(uint32_t new_prefix)
4966b3278c9SClaudio Imbrenda {
4976b3278c9SClaudio Imbrenda asm volatile(" spx %0" : : "Q" (new_prefix) : "memory");
4986b3278c9SClaudio Imbrenda }
4996b3278c9SClaudio Imbrenda
get_prefix(void)5006b3278c9SClaudio Imbrenda static inline uint32_t get_prefix(void)
5016b3278c9SClaudio Imbrenda {
5026b3278c9SClaudio Imbrenda uint32_t current_prefix;
5036b3278c9SClaudio Imbrenda
5046b3278c9SClaudio Imbrenda asm volatile(" stpx %0" : "=Q" (current_prefix));
5056b3278c9SClaudio Imbrenda return current_prefix;
5066b3278c9SClaudio Imbrenda }
5076b3278c9SClaudio Imbrenda
diag44(void)508*da49e291SNina Schoetterl-Glausch static inline void diag44(void)
509*da49e291SNina Schoetterl-Glausch {
510*da49e291SNina Schoetterl-Glausch asm volatile("diag 0,0,0x44\n");
511*da49e291SNina Schoetterl-Glausch }
512*da49e291SNina Schoetterl-Glausch
diag500(uint64_t val)513*da49e291SNina Schoetterl-Glausch static inline void diag500(uint64_t val)
514*da49e291SNina Schoetterl-Glausch {
515*da49e291SNina Schoetterl-Glausch asm volatile(
516*da49e291SNina Schoetterl-Glausch "lgr 2,%[val]\n"
517*da49e291SNina Schoetterl-Glausch "diag 0,0,0x500\n"
518*da49e291SNina Schoetterl-Glausch :
519*da49e291SNina Schoetterl-Glausch : [val] "d"(val)
520*da49e291SNina Schoetterl-Glausch : "r2"
521*da49e291SNina Schoetterl-Glausch );
522*da49e291SNina Schoetterl-Glausch }
523*da49e291SNina Schoetterl-Glausch
524cfb204f9SDavid Hildenbrand #endif
525