Lines Matching full:bits
30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
45 #define PCI_STATUS 0x06 /* 16 bits */
62 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
67 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
68 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
69 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
74 #define PCI_BIST 0x0f /* 8 bits */
83 * 1 bits are decoded.
85 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
86 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
87 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
88 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
89 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
90 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
107 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
114 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
115 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
116 #define PCI_MIN_GNT 0x3e /* 8 bits */
117 #define PCI_MAX_LAT 0x3f /* 8 bits */
222 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
281 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
284 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
303 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
304 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
305 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
306 #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
308 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
309 #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
440 #define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */
698 /* Same bits as above */
700 /* Same bits as above */
711 /* Same bits as above */
813 #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */
815 #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */