xref: /kvm-unit-tests/lib/x86/asm/debugreg.h (revision f1dcfd54130ca2b1851d46dffd7ffadbe5eb4a3b)
1a991ed2fSRoman Bolshakov /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2c865f654SCornelia Huck #ifndef _ASMX86_DEBUGREG_H_
3c865f654SCornelia Huck #define _ASMX86_DEBUGREG_H_
4a991ed2fSRoman Bolshakov 
5*f1dcfd54SSean Christopherson #include <bitops.h>
6a991ed2fSRoman Bolshakov 
7a991ed2fSRoman Bolshakov /*
8*f1dcfd54SSean Christopherson  * DR6_ACTIVE_LOW combines fixed-1 and active-low bits (e.g. RTM), and is also
9*f1dcfd54SSean Christopherson  * the init/reset value for DR6.
10a991ed2fSRoman Bolshakov  */
11*f1dcfd54SSean Christopherson #define DR6_ACTIVE_LOW	0xffff0ff0
12*f1dcfd54SSean Christopherson #define DR6_VOLATILE	0x0001e80f
13*f1dcfd54SSean Christopherson #define DR6_FIXED_1	(DR6_ACTIVE_LOW & ~DR6_VOLATILE)
14*f1dcfd54SSean Christopherson 
15*f1dcfd54SSean Christopherson #define DR6_TRAP0	BIT(0)		/* DR0 matched */
16*f1dcfd54SSean Christopherson #define DR6_TRAP1	BIT(1)		/* DR1 matched */
17*f1dcfd54SSean Christopherson #define DR6_TRAP2	BIT(2)		/* DR2 matched */
18*f1dcfd54SSean Christopherson #define DR6_TRAP3	BIT(3)		/* DR3 matched */
19*f1dcfd54SSean Christopherson #define DR6_TRAP_BITS	(DR6_TRAP0|DR6_TRAP1|DR6_TRAP2|DR6_TRAP3)
20*f1dcfd54SSean Christopherson 
21*f1dcfd54SSean Christopherson #define DR6_BUS_LOCK	BIT(11)		/* Bus lock	    0x800 */
22*f1dcfd54SSean Christopherson #define DR6_BD		BIT(13)		/* General Detect  0x2000 */
23*f1dcfd54SSean Christopherson #define DR6_BS		BIT(14)		/* Single-Step	   0x4000 */
24*f1dcfd54SSean Christopherson #define DR6_BT		BIT(15)		/* Task Switch	   0x8000 */
25*f1dcfd54SSean Christopherson #define DR6_RTM		BIT(16)		/* RTM / TSX	  0x10000 */
26*f1dcfd54SSean Christopherson 
27*f1dcfd54SSean Christopherson #define DR7_FIXED_1	0x00000400	/* init/reset value, too */
28*f1dcfd54SSean Christopherson #define DR7_VOLATILE	0xffff2bff
29*f1dcfd54SSean Christopherson #define DR7_BP_EN_MASK	0x000000ff
30*f1dcfd54SSean Christopherson #define DR7_LE		BIT(8)		/* Local Exact	    0x100 */
31*f1dcfd54SSean Christopherson #define DR7_GE		BIT(9)		/* Global Exact     0x200 */
32*f1dcfd54SSean Christopherson #define DR7_RTM		BIT(11)		/* RTM / TSX	    0x800 */
33*f1dcfd54SSean Christopherson #define DR7_GD		BIT(13)		/* General Detect  0x2000 */
34*f1dcfd54SSean Christopherson 
35*f1dcfd54SSean Christopherson /*
36*f1dcfd54SSean Christopherson  * Enable bits for DR0-D3.  Bits 0, 2, 4, and 6 are local enable bits (cleared
37*f1dcfd54SSean Christopherson  * by the CPU on task switch), bits 1, 3, 5, and 7 are global enable bits
38*f1dcfd54SSean Christopherson  * (never cleared by the CPU).
39*f1dcfd54SSean Christopherson  */
40*f1dcfd54SSean Christopherson #define DR7_LOCAL_ENABLE_DRx(x)		(BIT(0) << (x))
41*f1dcfd54SSean Christopherson #define DR7_GLOBAL_ENABLE_DRx(x)	(BIT(1) << (x))
42*f1dcfd54SSean Christopherson #define DR7_ENABLE_DRx(x) \
43*f1dcfd54SSean Christopherson 	(DR7_LOCAL_ENABLE_DRx(x) | DR7_GLOBAL_ENABLE_DRx(x))
44*f1dcfd54SSean Christopherson 
45*f1dcfd54SSean Christopherson #define DR7_GLOBAL_ENABLE_DR0	DR7_GLOBAL_ENABLE_DRx(0)
46*f1dcfd54SSean Christopherson #define DR7_GLOBAL_ENABLE_DR1	DR7_GLOBAL_ENABLE_DRx(1)
47*f1dcfd54SSean Christopherson #define DR7_GLOBAL_ENABLE_DR2	DR7_GLOBAL_ENABLE_DRx(2)
48*f1dcfd54SSean Christopherson #define DR7_GLOBAL_ENABLE_DR3	DR7_GLOBAL_ENABLE_DRx(3)
49*f1dcfd54SSean Christopherson 
50*f1dcfd54SSean Christopherson /* Condition/type of the breakpoint for DR0-3. */
51*f1dcfd54SSean Christopherson #define DR7_RW_TYPE_DRx(x, rw)	((rw) << (((x) * 4) + 16))
52*f1dcfd54SSean Christopherson #define DR7_EXECUTE_DRx(x)	DR7_RW_TYPE_DRx(x, 0)
53*f1dcfd54SSean Christopherson #define DR7_WRITE_DRx(x)	DR7_RW_TYPE_DRx(x, 1)
54*f1dcfd54SSean Christopherson #define DR7_PORT_IO_DRx(x)	DR7_RW_TYPE_DRx(x, 2)
55*f1dcfd54SSean Christopherson #define DR7_DATA_IO_DRx(x)	DR7_RW_TYPE_DRx(x, 3)	/* Read or Write */
56*f1dcfd54SSean Christopherson 
57*f1dcfd54SSean Christopherson /* Length of the breakpoint for DR0-3. */
58*f1dcfd54SSean Christopherson #define DR7_LEN_DRx(x, enc)	((enc) << (((x) * 4) + 18))
59*f1dcfd54SSean Christopherson #define DR7_LEN_1_DRx(x)	DR7_LEN_DRx(x, 0)
60*f1dcfd54SSean Christopherson #define DR7_LEN_2_DRx(x)	DR7_LEN_DRx(x, 1)
61*f1dcfd54SSean Christopherson #define DR7_LEN_4_DRx(x)	DR7_LEN_DRx(x, 3)
62*f1dcfd54SSean Christopherson #define DR7_LEN_8_DRx(x)	DR7_LEN_DRx(x, 2) /* Out of sequence, undefined for 32-bit CPUs. */
63a991ed2fSRoman Bolshakov 
64c865f654SCornelia Huck #endif /* _ASMX86_DEBUGREG_H_ */
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