27  * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that
1037  * @enable_ad:	Whether or not to enable Access/Dirty bits for EPT entries
1079  * @enable_ad:	Whether or not to enable Access/Dirty bits for EPT entries
1099 	 * accessed/dirty bits at 4K granularity.  in setup_ept()
1159 		test_skip("EPT AD bits not supported.");  in ept_enable_ad_bits_or_skip_test()
1508 		printf("\tEPT A/D bits are not supported");  in eptad_init()
2320  * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into
2362 	/* Mask undefined bits (which may later be defined in certain cases). */  in do_ept_violation()
2447  *	@pte_ad		Set the A/D bits on the guest PTE accordingly.
2477 	 * Now modify the access bits on the EPT entry for the GPA that the  in ept_access_paddr()
2669 	/* Making the entry non-present turns reserved bits into ignored. */  in ept_reserved_bit_at_level_nohuge()
2679 	/* Making the entry non-present turns reserved bits into ignored. */  in ept_reserved_bit_at_level_huge()
2689 	/* Making the entry non-present turns reserved bits into ignored. */  in ept_reserved_bit_at_level()
2875 	/* Reserved bits above maxphyaddr. */  in ept_access_test_reserved_bits()
2883 	/* Level-specific reserved bits. */  in ept_access_test_reserved_bits()
2915 	 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as  in ept_access_test_ignored_bits()
2916 	 * far as translation is concerned even if AD bits are enabled in the  in ept_access_test_ignored_bits()
2963 	 * When EPT AD bits are disabled, all accesses to guest paging  in ept_access_test_paddr_read_only_ad_disabled()
2966 	 * if the A/D bits have to be set.  in ept_access_test_paddr_read_only_ad_disabled()
2977 	/* AD bits disabled, so only writes try to update the D bit. */  in ept_access_test_paddr_read_only_ad_disabled()
2990 	 * When EPT AD bits are enabled, all accesses to guest paging  in ept_access_test_paddr_read_only_ad_enabled()
3031 	 * When EPT AD bits are disabled, all accesses to guest paging  in ept_access_test_paddr_read_execute_ad_disabled()
3034 	 * if the A/D bits have to be set.  in ept_access_test_paddr_read_execute_ad_disabled()
3045 	/* AD bits disabled, so only writes try to update the D bit. */  in ept_access_test_paddr_read_execute_ad_disabled()
3058 	 * When EPT AD bits are enabled, all accesses to guest paging  in ept_access_test_paddr_read_execute_ad_enabled()
3308 	 * VPID must not be more than 16 bits.  in invvpid_test()
3456 	 * test turning on bits that have a required setting.  in test_rsvd_ctl_bit_value()
3492  * Reserved bits in the pin-based VM-execution controls must be set
3509  * Reserved bits in the primary processor-based VM-execution controls
3527  * VM-execution control is 1, reserved bits in the secondary
3529  * consult the VMX capability MSRs to determine which bits are
3713  * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of
3715  * bits beyond the processor's physical-address width.
3729  * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of
3731  * bits beyond the processor's physical-address width.
3744  * - Bits 11:0 of the address must be 0.
3745  * - The address should not set any bits beyond the processor's
3767  *  - Bits 11:0 of the address must be 0.
3768  *  - The address should not set any bits beyond the processor's
3968  *	- range 0 - 255 (bits 15:8 are all 0).
3969  *	- Bits 5:0 of the posted-interrupt descriptor address are all 0.
3970  *	- The posted-interrupt descriptor address does not set any bits
4369 	/* Reserved bits in the field (30:12) are 0. */  in test_invalid_event_injection()
4370 	report_prefix_push("reserved bits clear");  in test_invalid_event_injection()
4386 	 * bits 31:16 of the VM-entry exception error-code field are 0.  in test_invalid_event_injection()
4513  *         "virtual-interrupt delivery" VM-execution control is 0, bits
4521  *          is 0, the value of bits 3:0 of the TPR threshold VM-execution
4522  *          control field must not be greater than the value of bits
4707  *     - The EPT memory type (bits 2:0) must be a value supported by the
4709  *     - Bits 5:3 (1 less than the EPT page-walk length) must indicate a
4715  *     - Reserved bits 11:7 and 63:N (where N is the processor's
4758 	 * Page walk length (bits 5:3).  Note, the value in VMCS.EPTP "is 1  in test_ept_eptp()
4800 	 * Reserved bits [11:7] and [63:N]  in test_ept_eptp()
4807 		report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu",  in test_ept_eptp()
4828 		report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu",  in test_ept_eptp()
4875  *    * Bits 11:0 of the address must be 0.
4876  *    * The address should not set any bits beyond the processor's
5205 	 * Set CS access rights bits for 32-bit protected mode:  in vmx_mtf_pdpte_test()
5237 	 * Bits 11:0   page offset  in vmx_mtf_pdpte_test()
5238 	 * Bits 20:12  entry into 512-entry page table  in vmx_mtf_pdpte_test()
5239 	 * Bits 29:21  entry into a 512-entry directory table  in vmx_mtf_pdpte_test()
5240 	 * Bits 31:30  entry into the page directory pointer table.  in vmx_mtf_pdpte_test()
5241 	 * Bits 63:32  zero  in vmx_mtf_pdpte_test()
5243 	 * As only 2 bits are needed to select the PDPTEs for the entire  in vmx_mtf_pdpte_test()
5265 	 * bits cleared. Note that permission bits from the PML4E and PDPTE  in vmx_mtf_pdpte_test()
5270 				   "PDPTE has invalid reserved bits");  in vmx_mtf_pdpte_test()
5337   *    - The lower 4 bits of the VM-entry MSR-load address must be 0.
5338   *      The address should not set any bits beyond the processor's
5342   *      should not set any bits beyond the processor's physical-address
5345   *      uses more bits than the processor's physical-address width.)
5360 	/* Check first 4 bits of VM-entry MSR-load address */  in test_entry_msr_load()
5463  *    - The lower 4 bits of the VM-exit MSR-store address must be 0.
5464  *      The address should not set any bits beyond the processor's
5468  *      should not set any bits beyond the processor's physical-address
5471  *      uses more bits than the processor's physical-address width.)
5473  * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits
5488 	/* Check first 4 bits of VM-exit MSR-store address */  in test_exit_msr_store()
6148 		report_skip("%s : Not all required APICv bits supported", __func__);  in apic_reg_virt_test()
6241 	 * the x2APIC registers are 32 bits. Notice:
6242 	 *   1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers.
6309 		/* Bits 31:8 are reserved. */  in get_x2apic_wr_val()
6922 		report_skip("%s : Not all required APICv bits supported", __func__);  in virt_x2apic_mode_test()
7052  *    be such that bits 63:52 and bits in the range 51:32 beyond the
7190 	 * Check reserved bits  in test_efer()
7218 	 * Check LMA and LME bits  in test_efer()
7241  * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the
7243  * the values of the LMA and LME bits in the field must each be that of
7256  * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the
7258  * the values of the LMA and LME bits in the field must each be that of
7644  *    RPL (bits 1:0) and the TI flag (bit 2) must be 0.
7711  *    - Bits 63:32 in the RIP field are 0.
7798  * If the "load debug controls" VM-entry control is 1, bits 63:32 in
7860  *   - Bits reserved in the IA32_BNDCFGS MSR must be 0.
7861  *   - The linear address in bits 63:12 must be canonical.
7920  *	guest" VM-execution control is 0, the RPL (bits 1:0) must equal
8026  *    - CS : Bits 63:32 of the address must be zero.
8027  *    - SS, DS, ES : If the register is usable, bits 63:32 of the address
8056 	 * Bits 63:32 in CS, SS, DS and ES base address must be zero  in test_guest_segment_base_addr_fields()
8378 	 * most definitely do not have any of bits 56:48 set).  in vmx_cr_load_test()
9295  * exception bits are properly accumulated into the exit qualification
9301 	 * We are going to set a few arbitrary bits in DR6 to verify that  in vmx_db_test()
9303 	 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into  in vmx_db_test()
9477 		report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__);  in vmx_eoi_bitmap_ioapic_scan_test()
9522 		report_skip("%s : Not all required APICv bits supported", __func__);  in vmx_hlt_with_rvi_test()
11221 		report_skip("%s : Not all required APICv bits supported", __func__);  in vmx_basic_vid_test()
11289 		report_skip("%s : Not all required APICv bits supported", __func__);  in vmx_eoi_virt_test()
11336 		report_skip("%s : Not all required APICv bits supported", __func__);  in vmx_posted_interrupts_test()