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/qemu/hw/smbios/
H A Dsmbios_type_38.c31 SMBIOS_BUILD_TABLE_PRE(38, 0x3000, true); in smbios_build_one_type_38()
37 t->nv_storage_device_address = 0; in smbios_build_one_type_38()
57 t->base_address_modifier = 0; in smbios_build_one_type_38()
79 t->interrupt_number = 0; in smbios_build_one_type_38()
101 memset(&info, 0, sizeof(info)); in smbios_add_ipmi_devices()
/qemu/include/hw/pci-host/
H A Dpnv_phb4.h70 #define PNV_PHB4_NUM_REGS (0x3000 >> 3)
76 #define PNV_PHB4_VERSION 0x000000a400000002ull
77 #define PNV_PHB4_DEVICE_ID 0x04c1
79 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
116 #define PHB4_PEC_PCI_STK_REGS_COUNT 0xf
121 #define PHB4_PEC_NEST_STK_REGS_COUNT 0x18
182 #define PHB4_PEC_NEST_REGS_COUNT 0xf
187 #define PHB4_PEC_PCI_REGS_COUNT 0x3
225 #define PNV_PHB5_VERSION 0x000000a500000002ull
H A Dpnv_phb4_regs.h32 * stacks, thus for PEC2, the global registers are at offset 0, the
33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc....
36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc..
38 #define PEC_STACK_OFFSET 0x40
41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00
42 #define PEC_NEST_DROP_PRIO_CTRL 0x01
43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02
44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03
45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04
46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05
[all …]
/qemu/include/hw/ppc/
H A Dmac_dbdma.h53 #define DBDMA_CONTROL 0x00
54 #define DBDMA_STATUS 0x01
55 #define DBDMA_CMDPTR_HI 0x02
56 #define DBDMA_CMDPTR_LO 0x03
57 #define DBDMA_INTR_SEL 0x04
58 #define DBDMA_BRANCH_SEL 0x05
59 #define DBDMA_WAIT_SEL 0x06
60 #define DBDMA_XFER_MODE 0x07
61 #define DBDMA_DATA2PTR_HI 0x08
62 #define DBDMA_DATA2PTR_LO 0x09
[all …]
H A Dspapr_nested.h7 #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL 0x0006 /* Process Table */
14 /* RESERVED 0x0007 - 0x07FF */
15 #define GSB_L0_GUEST_HEAP_INUSE 0x0800 /* Guest Management Heap Size */
16 #define GSB_L0_GUEST_HEAP_MAX 0x0801 /* Guest Management Heap Max Size */
[all …]
/qemu/include/hw/arm/
H A Draspi_platform.h67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
[all …]
/qemu/tests/qtest/
H A Driscv-iommu-test.c62 g_assert_cmpuint(cap & RISCV_IOMMU_CAP_VERSION, ==, 0x10); in test_reg_reset()
65 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQEN, ==, 0); in test_reg_reset()
66 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CIE, ==, 0); in test_reg_reset()
67 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQON, ==, 0); in test_reg_reset()
68 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_BUSY, ==, 0); in test_reg_reset()
71 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQEN, ==, 0); in test_reg_reset()
72 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FIE, ==, 0); in test_reg_reset()
73 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQON, ==, 0); in test_reg_reset()
74 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_BUSY, ==, 0); in test_reg_reset()
77 g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PQEN, ==, 0); in test_reg_reset()
[all …]
/qemu/tests/unit/
H A Dtest-logging.c38 qemu_set_dfilter_ranges("0x1000+0x100", &error_abort); in test_parse_range()
40 g_assert_false(qemu_log_in_addr_range(0xfff)); in test_parse_range()
41 g_assert(qemu_log_in_addr_range(0x1000)); in test_parse_range()
42 g_assert(qemu_log_in_addr_range(0x1001)); in test_parse_range()
43 g_assert(qemu_log_in_addr_range(0x10ff)); in test_parse_range()
44 g_assert_false(qemu_log_in_addr_range(0x1100)); in test_parse_range()
46 qemu_set_dfilter_ranges("0x1000-0x100", &error_abort); in test_parse_range()
48 g_assert_false(qemu_log_in_addr_range(0x1001)); in test_parse_range()
49 g_assert(qemu_log_in_addr_range(0x1000)); in test_parse_range()
50 g_assert(qemu_log_in_addr_range(0x0f01)); in test_parse_range()
[all …]
/qemu/hw/hyperv/
H A Dhyperv_testdev.c149 case 0: in msg_handler()
244 return 0; in hv_test_dev_read()
251 uint8_t sint = data & 0xFF; in hv_test_dev_write()
252 uint8_t vp_index = (data >> 8ULL) & 0xFF; in hv_test_dev_write()
253 uint8_t ctl = (data >> 16ULL) & 0xFF; in hv_test_dev_write()
254 uint8_t conn_id = (data >> 24ULL) & 0xFF; in hv_test_dev_write()
303 memory_region_add_subregion(io, 0x3000, &dev->sint_control); in hv_test_dev_realizefn()
/qemu/docs/devel/
H A Dvfio-iommufd.rst151 …qemu-system-x86_64: vfio_container_dma_map(0x560cb6cb1620, 0xe000000021000, 0x3000, 0x7f32ed55c000…
/qemu/hw/usb/
H A Dhcd-xhci-pci.c35 #define OFF_MSIX_TABLE 0x3000
36 #define OFF_MSIX_PBA 0x3800
65 if (n == 0 && in xhci_pci_intr_raise()
93 * Forces all events onto interrupter/event ring 0 in pin-based IRQ mode. in xhci_pci_intr_mapping_conditional()
113 for (intr = 0; intr < s->xhci.numintrs; intr++) { in xhci_pci_vmstate_post_load()
120 return 0; in xhci_pci_vmstate_post_load()
129 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ in usb_xhci_pci_realize()
130 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ in usb_xhci_pci_realize()
131 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; in usb_xhci_pci_realize()
132 dev->config[0x60] = 0x30; /* release number */ in usb_xhci_pci_realize()
[all …]
H A Ddev-mtp.c50 CMD_GET_DEVICE_INFO = 0x1001,
51 CMD_OPEN_SESSION = 0x1002,
52 CMD_CLOSE_SESSION = 0x1003,
53 CMD_GET_STORAGE_IDS = 0x1004,
54 CMD_GET_STORAGE_INFO = 0x1005,
55 CMD_GET_NUM_OBJECTS = 0x1006,
56 CMD_GET_OBJECT_HANDLES = 0x1007,
57 CMD_GET_OBJECT_INFO = 0x1008,
58 CMD_GET_OBJECT = 0x1009,
59 CMD_DELETE_OBJECT = 0x100b,
[all …]
/qemu/hw/misc/
H A Daspeed_i3c.c21 REG32(I3C1_REG0, 0x10)
22 REG32(I3C1_REG1, 0x14)
23 FIELD(I3C1_REG1, I2C_MODE, 0, 1)
25 REG32(I3C2_REG0, 0x20)
26 REG32(I3C2_REG1, 0x24)
27 FIELD(I3C2_REG1, I2C_MODE, 0, 1)
29 REG32(I3C3_REG0, 0x30)
30 REG32(I3C3_REG1, 0x34)
31 FIELD(I3C3_REG1, I2C_MODE, 0, 1)
33 REG32(I3C4_REG0, 0x40)
[all …]
/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_mmu.S6 #define BASE 0x20000000
7 #define TLB_BASE 0x80000000
23 clean_tlb_way 0, 0x00001000, 4
24 clean_tlb_way 1, 0x00001000, 4
25 clean_tlb_way 2, 0x00001000, 4
26 clean_tlb_way 3, 0x00001000, 4
27 clean_tlb_way 4, 0x00100000, 4
28 movi a2, 0x00000007
30 movi a2, 0x00000008
32 movi a2, 0x00000009
[all …]
/qemu/hw/virtio/
H A Dvirtio-nsm.c22 #define NSM_REQUEST_MAX_SIZE 0x1000
23 #define NSM_RESPONSE_BUF_SIZE 0x3000
27 NSM_SUCCESS = 0,
105 if (len == 0) { in error_response()
162 if (len == 0) { in handle_get_random()
201 * value = Uint8(0),
203 * value = Uint8(0)
212 uint16_t locked_pcrs_cnt = 0; in handle_describe_nsm()
239 for (uint8_t i = 0; i < NSM_MAX_PCRS; ++i) { in handle_describe_nsm()
265 if (len == 0) { in handle_describe_nsm()
[all …]
/qemu/hw/arm/
H A Dmusca.c110 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); in OBJECT_DECLARE_TYPE()
150 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); in make_unimp_dev()
170 .addr = 0x00200000,
171 .size = 0x00800000,
175 .addr = 0x00000000,
176 .size = 0x00200000,
183 .addr = 0x00000000,
184 .size = 0x02000000,
188 .addr = 0x0a400000,
189 .size = 0x00080000,
[all …]
/qemu/hw/pci/
H A Dshpc.c21 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
22 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
23 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */
24 #define SHPC_NSLOTS 0x0C /* 1 byte */
25 #define SHPC_FIRST_DEV 0x0D /* 1 byte */
26 #define SHPC_PHYS_SLOT 0x0E /* 2 byte */
27 #define SHPC_PHYS_NUM_MAX 0x7ff
28 #define SHPC_PHYS_NUM_UP 0x2000
29 #define SHPC_PHYS_MRL 0x4000
30 #define SHPC_PHYS_BUTTON 0x8000
[all …]
/qemu/hw/net/
H A Dnpcm_gmac.c39 REG32(NPCM_DMA_BUS_MODE, 0x1000)
40 REG32(NPCM_DMA_XMT_POLL_DEMAND, 0x1004)
41 REG32(NPCM_DMA_RCV_POLL_DEMAND, 0x1008)
42 REG32(NPCM_DMA_RX_BASE_ADDR, 0x100c)
43 REG32(NPCM_DMA_TX_BASE_ADDR, 0x1010)
44 REG32(NPCM_DMA_STATUS, 0x1014)
45 REG32(NPCM_DMA_CONTROL, 0x1018)
46 REG32(NPCM_DMA_INTR_ENA, 0x101c)
47 REG32(NPCM_DMA_MISSED_FRAME_CTR, 0x1020)
48 REG32(NPCM_DMA_HOST_TX_DESC, 0x1048)
[all …]
H A Dsungem.c30 #define SUNGEM_MMIO_SIZE 0x200000
33 #define SUNGEM_MMIO_GREG_SIZE 0x2000
35 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
37 #define GREG_STAT 0x000CUL /* Status Register */
38 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
39 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
40 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
41 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
42 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
43 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
[all …]
/qemu/include/standard-headers/linux/
H A Dpci_regs.h38 #define PCI_VENDOR_ID 0x00 /* 16 bits */
39 #define PCI_DEVICE_ID 0x02 /* 16 bits */
40 #define PCI_COMMAND 0x04 /* 16 bits */
41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
45 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
/qemu/hw/intc/
H A Daspeed_intc.c20 * values below are offset by - 0x1000 from datasheet
21 * because its memory region is start at 0x1000
24 REG32(GICINT128_EN, 0x000)
25 REG32(GICINT128_STATUS, 0x004)
26 REG32(GICINT129_EN, 0x100)
27 REG32(GICINT129_STATUS, 0x104)
28 REG32(GICINT130_EN, 0x200)
29 REG32(GICINT130_STATUS, 0x204)
30 REG32(GICINT131_EN, 0x300)
31 REG32(GICINT131_STATUS, 0x304)
[all …]
H A Driscv_aplic.c45 #define APLIC_DOMAINCFG 0x0000
46 #define APLIC_DOMAINCFG_RDONLY 0x80000000
49 #define APLIC_DOMAINCFG_BE (1 << 0)
51 #define APLIC_SOURCECFG_BASE 0x0004
53 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
54 #define APLIC_SOURCECFG_SM_MASK 0x00000007
55 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
56 #define APLIC_SOURCECFG_SM_DETACH 0x1
57 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
58 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
[all …]
/qemu/target/sh4/
H A Dtranslate.c98 for (i = 0; i < 24; i++) { in sh4_translate_init()
154 for (i = 0; i < 32; i++) in sh4_translate_init()
165 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
167 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
169 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
171 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
172 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
177 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
180 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
183 qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
[all …]
/qemu/hw/dma/
H A Domap_dma.c127 #define TIMEOUT_INTR (1 << 0)
154 a->src = ch->addr[0]; in omap_dma_channel_load()
159 a->frame = 0; in omap_dma_channel_load()
160 a->element = 0; in omap_dma_channel_load()
161 a->pck_element = 0; in omap_dma_channel_load()
168 for (i = 0; i < 2; i ++) in omap_dma_channel_load()
171 a->elem_delta[i] = 0; in omap_dma_channel_load()
172 a->frame_delta[i] = 0; in omap_dma_channel_load()
176 a->frame_delta[i] = 0; in omap_dma_channel_load()
180 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
[all …]

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