Lines Matching +full:0 +full:x3000
45 #define APLIC_DOMAINCFG 0x0000
46 #define APLIC_DOMAINCFG_RDONLY 0x80000000
49 #define APLIC_DOMAINCFG_BE (1 << 0)
51 #define APLIC_SOURCECFG_BASE 0x0004
53 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
54 #define APLIC_SOURCECFG_SM_MASK 0x00000007
55 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
56 #define APLIC_SOURCECFG_SM_DETACH 0x1
57 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
58 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
59 #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
60 #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
62 #define APLIC_MMSICFGADDR 0x1bc0
63 #define APLIC_MMSICFGADDRH 0x1bc4
64 #define APLIC_SMSICFGADDR 0x1bc8
65 #define APLIC_SMSICFGADDRH 0x1bcc
68 #define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
70 #define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
72 #define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
74 #define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
76 #define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
107 #define APLIC_SETIP_BASE 0x1c00
108 #define APLIC_SETIPNUM 0x1cdc
110 #define APLIC_CLRIP_BASE 0x1d00
111 #define APLIC_CLRIPNUM 0x1ddc
113 #define APLIC_SETIE_BASE 0x1e00
114 #define APLIC_SETIENUM 0x1edc
116 #define APLIC_CLRIE_BASE 0x1f00
117 #define APLIC_CLRIENUM 0x1fdc
119 #define APLIC_SETIPNUM_LE 0x2000
120 #define APLIC_SETIPNUM_BE 0x2004
122 #define APLIC_ISTATE_PENDING (1U << 0)
128 #define APLIC_GENMSI 0x3000
130 #define APLIC_TARGET_BASE 0x3004
132 #define APLIC_TARGET_HART_IDX_MASK 0x3fff
134 #define APLIC_TARGET_GUEST_IDX_MASK 0x3f
135 #define APLIC_TARGET_IPRIO_MASK 0xff
136 #define APLIC_TARGET_EIID_MASK 0x7ff
138 #define APLIC_IDC_BASE 0x4000
141 #define APLIC_IDC_IDELIVERY 0x00
143 #define APLIC_IDC_IFORCE 0x04
145 #define APLIC_IDC_ITHRESHOLD 0x08
147 #define APLIC_IDC_TOPI 0x18
149 #define APLIC_IDC_TOPI_ID_MASK 0x3ff
150 #define APLIC_IDC_TOPI_PRIO_MASK 0xff
152 #define APLIC_IDC_CLAIMI 0x1c
185 aplic->kvm_msicfgaddr = extract64(addr, 0, 32); in riscv_aplic_set_kvm_msicfgaddr()
211 raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0; in riscv_aplic_irq_rectified_val()
213 sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0; in riscv_aplic_irq_rectified_val()
221 uint32_t i, irq, rectified_val, ret = 0; in riscv_aplic_read_input_word()
223 for (i = 0; i < 32; i++) { in riscv_aplic_read_input_word()
236 uint32_t i, irq, ret = 0; in riscv_aplic_read_pending_word()
238 for (i = 0; i < 32; i++) { in riscv_aplic_read_pending_word()
244 ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i; in riscv_aplic_read_pending_word()
265 if ((irq <= 0) || (aplic->num_irqs <= irq)) { in riscv_aplic_set_pending()
307 for (i = 0; i < 32; i++) { in riscv_aplic_set_pending_word()
322 uint32_t i, irq, ret = 0; in riscv_aplic_read_enabled_word()
324 for (i = 0; i < 32; i++) { in riscv_aplic_read_enabled_word()
330 ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i; in riscv_aplic_read_enabled_word()
351 if ((irq <= 0) || (aplic->num_irqs <= irq)) { in riscv_aplic_set_enabled()
374 for (i = 0; i < 32; i++) { in riscv_aplic_set_enabled_word()
469 guest_idx = 0; in riscv_aplic_msi_irq_update()
484 return 0; in riscv_aplic_idc_topi()
516 return 0; in riscv_aplic_idc_topi()
542 aplic->iforce[idc] = 0; in riscv_aplic_idc_claimi()
544 return 0; in riscv_aplic_idc_claimi()
569 assert((0 < irq) && (irq < aplic->num_irqs)); in riscv_aplic_request()
583 if ((level > 0) && !(state & APLIC_ISTATE_INPUT) && in riscv_aplic_request()
590 if ((level <= 0) && (state & APLIC_ISTATE_INPUT) && in riscv_aplic_request()
597 if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) { in riscv_aplic_request()
603 if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) { in riscv_aplic_request()
612 if (level <= 0) { in riscv_aplic_request()
635 if ((addr & 0x3) != 0) { in riscv_aplic_read()
641 (aplic->msimode ? APLIC_DOMAINCFG_DM : 0); in riscv_aplic_read()
663 return (aplic->num_children) ? aplic->smsicfgaddr : 0; in riscv_aplic_read()
666 return (aplic->num_children) ? aplic->smsicfgaddrH : 0; in riscv_aplic_read()
672 return 0; in riscv_aplic_read()
678 return 0; in riscv_aplic_read()
684 return 0; in riscv_aplic_read()
687 return 0; in riscv_aplic_read()
689 return 0; in riscv_aplic_read()
691 return 0; in riscv_aplic_read()
693 return 0; in riscv_aplic_read()
695 return (aplic->msimode) ? aplic->genmsi : 0; in riscv_aplic_read()
721 "%s: Invalid register read 0x%" HWADDR_PRIx "\n", in riscv_aplic_read()
723 return 0; in riscv_aplic_read()
733 if ((addr & 0x3) != 0) { in riscv_aplic_write()
745 value = 0; in riscv_aplic_write()
754 (aplic->sourcecfg[irq] == 0)) { in riscv_aplic_write()
827 0, in riscv_aplic_write()
845 aplic->idelivery[idc] = value & 0x1; in riscv_aplic_write()
848 aplic->iforce[idc] = value & 0x1; in riscv_aplic_write()
866 for (idc = 0; idc < aplic->num_harts; idc++) { in riscv_aplic_write()
878 "%s: Invalid register write 0x%" HWADDR_PRIx "\n", in riscv_aplic_write()
901 for (i = 0; i < aplic->num_harts; i++) { in riscv_aplic_realize()
906 (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { in riscv_aplic_realize()
923 for (i = 0; i < aplic->num_irqs; i++) { in riscv_aplic_realize()
956 DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0),
957 DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0),
958 DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0),
959 DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0),
960 DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0),
961 DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0),
962 DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0),
979 num_irqs, 0,
982 num_irqs, 0,
985 num_irqs, 0,
988 num_harts, 0,
991 num_harts, 0,
994 num_harts, 0,
1074 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); in riscv_aplic_create()
1077 for (i = 0; i < num_harts; i++) { in riscv_aplic_create()