Lines Matching +full:0 +full:x3000
21 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
22 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
23 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */
24 #define SHPC_NSLOTS 0x0C /* 1 byte */
25 #define SHPC_FIRST_DEV 0x0D /* 1 byte */
26 #define SHPC_PHYS_SLOT 0x0E /* 2 byte */
27 #define SHPC_PHYS_NUM_MAX 0x7ff
28 #define SHPC_PHYS_NUM_UP 0x2000
29 #define SHPC_PHYS_MRL 0x4000
30 #define SHPC_PHYS_BUTTON 0x8000
31 #define SHPC_SEC_BUS 0x10 /* 2 bytes */
32 #define SHPC_SEC_BUS_33 0x0
33 #define SHPC_SEC_BUS_66 0x1 /* Unused */
34 #define SHPC_SEC_BUS_MASK 0x7
35 #define SHPC_MSI_CTL 0x12 /* 1 byte */
36 #define SHPC_PROG_IFC 0x13 /* 1 byte */
37 #define SHPC_PROG_IFC_1_0 0x1
38 #define SHPC_CMD_CODE 0x14 /* 1 byte */
39 #define SHPC_CMD_TRGT 0x15 /* 1 byte */
40 #define SHPC_CMD_TRGT_MIN 0x1
41 #define SHPC_CMD_TRGT_MAX 0x1f
42 #define SHPC_CMD_STATUS 0x16 /* 2 bytes */
43 #define SHPC_CMD_STATUS_BUSY 0x1
44 #define SHPC_CMD_STATUS_MRL_OPEN 0x2
45 #define SHPC_CMD_STATUS_INVALID_CMD 0x4
46 #define SHPC_CMD_STATUS_INVALID_MODE 0x8
47 #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
48 #define SHPC_INT_COMMAND 0x1
49 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
50 #define SHPC_SERR_INT 0x20 /* 4 bytes */
51 #define SHPC_INT_DIS 0x1
52 #define SHPC_SERR_DIS 0x2
53 #define SHPC_CMD_INT_DIS 0x4
54 #define SHPC_ARB_SERR_DIS 0x8
55 #define SHPC_CMD_DETECTED 0x10000
56 #define SHPC_ARB_DETECTED 0x20000
57 /* 4 bytes * slot # (start from 0) */
58 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
60 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
63 #define SHPC_SLOT_STATE_MASK 0x03
67 #define SHPC_STATE_NO 0x0
68 #define SHPC_STATE_PWRONLY 0x1
69 #define SHPC_STATE_ENABLED 0x2
70 #define SHPC_STATE_DISABLED 0x3
72 #define SHPC_SLOT_PWR_LED_MASK 0xC
75 #define SHPC_SLOT_ATTN_LED_MASK 0x30
79 #define SHPC_LED_NO 0x0
80 #define SHPC_LED_ON 0x1
81 #define SHPC_LED_BLINK 0x2
82 #define SHPC_LED_OFF 0x3
84 #define SHPC_SLOT_STATUS_PWR_FAULT 0x40
85 #define SHPC_SLOT_STATUS_BUTTON 0x80
86 #define SHPC_SLOT_STATUS_MRL_OPEN 0x100
87 #define SHPC_SLOT_STATUS_66 0x200
88 #define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
89 #define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
90 #define SHPC_SLOT_STATUS_PRSNT_25W 0x1
91 #define SHPC_SLOT_STATUS_PRSNT_15W 0x2
92 #define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
94 #define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
98 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
100 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
101 #define SHPC_SLOT_EVENT_PRESENCE 0x01
102 #define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
103 #define SHPC_SLOT_EVENT_BUTTON 0x04
104 #define SHPC_SLOT_EVENT_MRL 0x08
105 #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
107 #define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
108 #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
116 /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
176 int level = 0; in shpc_interrupt_update()
178 uint32_t int_locator = 0; in shpc_interrupt_update()
181 for (slot = 0; slot < shpc->nslots; ++slot) { in shpc_interrupt_update()
194 level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0; in shpc_interrupt_update()
196 msi_notify(d, 0); in shpc_interrupt_update()
220 memset(shpc->config, 0, SHPC_SIZEOF(d)); in shpc_reset()
223 pci_set_long(shpc->config + SHPC_SLOTS_66, 0); in shpc_reset()
224 pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0)); in shpc_reset()
226 SHPC_IDX_TO_PHYSICAL(0) | in shpc_reset()
236 for (i = 0; i < shpc->nslots; ++i) { in shpc_reset()
245 if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) { in shpc_reset()
247 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN); in shpc_reset()
259 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66); in shpc_reset()
262 shpc->msi_requested = 0; in shpc_reset()
277 for (devfn = PCI_DEVFN(pci_slot, 0); in shpc_free_devices_in_slot()
338 DEVICE(shpc->sec_bus->devices[PCI_DEVFN(pci_slot, 0)]); in shpc_slot_command()
382 case 0x00 ... 0x3f: in shpc_command()
389 case 0x40 ... 0x47: in shpc_command()
393 case 0x48: in shpc_command()
396 for (i = 0; i < shpc->nslots; ++i) { in shpc_command()
403 for (i = 0; i < shpc->nslots; ++i) { in shpc_command()
413 case 0x49: in shpc_command()
417 for (i = 0; i < shpc->nslots; ++i) { in shpc_command()
424 for (i = 0; i < shpc->nslots; ++i) { in shpc_command()
452 for (i = 0; i < l; val >>= 8, ++i) { in shpc_write()
468 uint64_t val = 0x0; in shpc_read()
478 #define SHPC_CAP_LENGTH 0x08
479 #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
480 #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
481 #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
482 #define SHPC_CAP_CSP_MASK 0x4
483 #define SHPC_CAP_CIP_MASK 0x8
504 0, SHPC_CAP_LENGTH, in shpc_cap_add_config()
506 if (config_offset < 0) { in shpc_cap_add_config()
511 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); in shpc_cap_add_config()
512 pci_set_byte(config + SHPC_CAP_CxP, 0); in shpc_cap_add_config()
513 pci_set_long(config + SHPC_CAP_DWORD_DATA, 0); in shpc_cap_add_config()
516 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); in shpc_cap_add_config()
517 pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); in shpc_cap_add_config()
518 return 0; in shpc_cap_add_config()
552 if (pci_slot < SHPC_IDX_TO_PCI(0) || *slot >= shpc->nslots) { in shpc_device_get_slot()
555 pci_slot, SHPC_IDX_TO_PCI(0), in shpc_device_get_slot()
578 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); in shpc_device_plug_cb()
587 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); in shpc_device_plug_cb()
599 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); in shpc_device_plug_cb()
642 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); in shpc_device_unplug_request_cb()
660 return 0; in shpc_init()
677 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff); in shpc_init()
688 for (i = 0; i < nslots; ++i) { in shpc_init()
716 return 0; in shpc_init()
768 return 0; in shpc_save()
780 d->shpc->msi_requested = 0; in shpc_load()
782 return 0; in shpc_load()