Lines Matching +full:0 +full:x3000
21 REG32(I3C1_REG0, 0x10)
22 REG32(I3C1_REG1, 0x14)
23 FIELD(I3C1_REG1, I2C_MODE, 0, 1)
25 REG32(I3C2_REG0, 0x20)
26 REG32(I3C2_REG1, 0x24)
27 FIELD(I3C2_REG1, I2C_MODE, 0, 1)
29 REG32(I3C3_REG0, 0x30)
30 REG32(I3C3_REG1, 0x34)
31 FIELD(I3C3_REG1, I2C_MODE, 0, 1)
33 REG32(I3C4_REG0, 0x40)
34 REG32(I3C4_REG1, 0x44)
35 FIELD(I3C4_REG1, I2C_MODE, 0, 1)
37 REG32(I3C5_REG0, 0x50)
38 REG32(I3C5_REG1, 0x54)
39 FIELD(I3C5_REG1, I2C_MODE, 0, 1)
41 REG32(I3C6_REG0, 0x60)
42 REG32(I3C6_REG1, 0x64)
43 FIELD(I3C6_REG1, I2C_MODE, 0, 1)
47 REG32(DEVICE_CTRL, 0x00)
48 REG32(DEVICE_ADDR, 0x04)
49 REG32(HW_CAPABILITY, 0x08)
50 REG32(COMMAND_QUEUE_PORT, 0x0c)
51 REG32(RESPONSE_QUEUE_PORT, 0x10)
52 REG32(RX_TX_DATA_PORT, 0x14)
53 REG32(IBI_QUEUE_STATUS, 0x18)
54 REG32(IBI_QUEUE_DATA, 0x18)
55 REG32(QUEUE_THLD_CTRL, 0x1c)
56 REG32(DATA_BUFFER_THLD_CTRL, 0x20)
57 REG32(IBI_QUEUE_CTRL, 0x24)
58 REG32(IBI_MR_REQ_REJECT, 0x2c)
59 REG32(IBI_SIR_REQ_REJECT, 0x30)
60 REG32(RESET_CTRL, 0x34)
61 REG32(SLV_EVENT_CTRL, 0x38)
62 REG32(INTR_STATUS, 0x3c)
63 REG32(INTR_STATUS_EN, 0x40)
64 REG32(INTR_SIGNAL_EN, 0x44)
65 REG32(INTR_FORCE, 0x48)
66 REG32(QUEUE_STATUS_LEVEL, 0x4c)
67 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)
68 REG32(PRESENT_STATE, 0x54)
69 REG32(CCC_DEVICE_STATUS, 0x58)
70 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c)
72 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16)
73 REG32(DEV_CHAR_TABLE_POINTER, 0x60)
74 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c)
75 REG32(SLV_MIPI_PID_VALUE, 0x70)
76 REG32(SLV_PID_VALUE, 0x74)
77 REG32(SLV_CHAR_CTRL, 0x78)
78 REG32(SLV_MAX_LEN, 0x7c)
79 REG32(MAX_READ_TURNAROUND, 0x80)
80 REG32(MAX_DATA_SPEED, 0x84)
81 REG32(SLV_DEBUG_STATUS, 0x88)
82 REG32(SLV_INTR_REQ, 0x8c)
83 REG32(DEVICE_CTRL_EXTENDED, 0xb0)
84 REG32(SCL_I3C_OD_TIMING, 0xb4)
85 REG32(SCL_I3C_PP_TIMING, 0xb8)
86 REG32(SCL_I2C_FM_TIMING, 0xbc)
87 REG32(SCL_I2C_FMP_TIMING, 0xc0)
88 REG32(SCL_EXT_LCNT_TIMING, 0xc8)
89 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc)
90 REG32(BUS_FREE_TIMING, 0xd4)
91 REG32(BUS_IDLE_TIMING, 0xd8)
92 REG32(I3C_VER_ID, 0xe0)
93 REG32(I3C_VER_TYPE, 0xe4)
94 REG32(EXTENDED_CAPABILITY, 0xe8)
95 REG32(SLAVE_CONFIG, 0xec)
98 [R_HW_CAPABILITY] = 0x000e00bf,
99 [R_QUEUE_THLD_CTRL] = 0x01000101,
100 [R_I3C_VER_ID] = 0x3130302a,
101 [R_I3C_VER_TYPE] = 0x6c633033,
102 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280,
103 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200,
104 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
105 [R_SLV_MAX_LEN] = 0x00ff00ff,
117 value = 0; in aspeed_i3c_device_read()
153 "%s: write to readonly register[0x%02" HWADDR_PRIx in aspeed_i3c_device_write()
154 "] = 0x%08" PRIx64 "\n", in aspeed_i3c_device_write()
205 uint64_t val = 0; in aspeed_i3c_read()
235 "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx in aspeed_i3c_write()
243 "]=0x%08" PRIx64 "\n", in aspeed_i3c_write()
268 memset(s->regs, 0, sizeof(s->regs)); in aspeed_i3c_reset()
276 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { in aspeed_i3c_instance_init()
289 TYPE_ASPEED_I3C ".container", 0x8000); in aspeed_i3c_realize()
296 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); in aspeed_i3c_realize()
298 for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { in aspeed_i3c_realize()
312 * X = 0, 1, 2, 3, 4, 5 in aspeed_i3c_realize()
313 * Offset of I3C0 = 0x2000 in aspeed_i3c_realize()
314 * Offset of I3C1 = 0x3000 in aspeed_i3c_realize()
315 * Offset of I3C2 = 0x4000 in aspeed_i3c_realize()
316 * Offset of I3C3 = 0x5000 in aspeed_i3c_realize()
317 * Offset of I3C4 = 0x6000 in aspeed_i3c_realize()
318 * Offset of I3C5 = 0x7000 in aspeed_i3c_realize()
321 0x2000 + i * 0x1000, &s->devices[i].mr); in aspeed_i3c_realize()
327 DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0),