62     g_assert_cmpuint(cap & RISCV_IOMMU_CAP_VERSION, ==, 0x10);  in test_reg_reset()
65     g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQEN, ==, 0);  in test_reg_reset()
66     g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CIE, ==, 0);  in test_reg_reset()
67     g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQON, ==, 0);  in test_reg_reset()
68     g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_BUSY, ==, 0);  in test_reg_reset()
71     g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQEN, ==, 0);  in test_reg_reset()
72     g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FIE, ==, 0);  in test_reg_reset()
73     g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQON, ==, 0);  in test_reg_reset()
74     g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_BUSY, ==, 0);  in test_reg_reset()
77     g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PQEN, ==, 0);  in test_reg_reset()
78     g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PIE, ==, 0);  in test_reg_reset()
79     g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PQON, ==, 0);  in test_reg_reset()
80     g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_BUSY, ==, 0);  in test_reg_reset()
83     g_assert_cmpuint(reg & RISCV_IOMMU_DDTP_BUSY, ==, 0);  in test_reg_reset()
88     g_assert_cmpuint(reg, ==, 0);  in test_reg_reset()
127     g_assert_cmpuint(reg64 & RISCV_IOMMU_CAP_VERSION, ==, 0x10);  in test_iommu_init_queues()
130      * Program the command queue. Write 0xF to civ, fiv, pmiv and  in test_iommu_init_queues()
134     riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_IVEC, 0xFFFF);  in test_iommu_init_queues()
136     g_assert_cmpuint(reg & RISCV_IOMMU_REG_IVEC_CIV, ==, 0x3);  in test_iommu_init_queues()
137     g_assert_cmpuint(reg & RISCV_IOMMU_REG_IVEC_FIV, ==, 0x30);  in test_iommu_init_queues()
138     g_assert_cmpuint(reg & RISCV_IOMMU_REG_IVEC_PMIV, ==, 0x300);  in test_iommu_init_queues()
139     g_assert_cmpuint(reg & RISCV_IOMMU_REG_IVEC_PIV, ==, 0x3000);  in test_iommu_init_queues()
143     reg64 = 0;  in test_iommu_init_queues()
150     /* cqt = 0, cqcsr.cqen = 1, poll cqcsr.cqon until it reads 1 */  in test_iommu_init_queues()
151     riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_CQT, 0);  in test_iommu_init_queues()
164     reg64 = 0;  in test_iommu_init_queues()
171     /* fqt = 0, fqcsr.fqen = 1, poll fqcsr.fqon until it reads 1 */  in test_iommu_init_queues()
172     riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_FQT, 0);  in test_iommu_init_queues()
185     reg64 = 0;  in test_iommu_init_queues()
192     /* pqt = 0, pqcsr.pqen = 1, poll pqcsr.pqon until it reads 1 */  in test_iommu_init_queues()
193     riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_PQT, 0);  in test_iommu_init_queues()