Lines Matching +full:0 +full:x3000
30 #define SUNGEM_MMIO_SIZE 0x200000
33 #define SUNGEM_MMIO_GREG_SIZE 0x2000
35 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
37 #define GREG_STAT 0x000CUL /* Status Register */
38 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
39 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
40 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
41 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
42 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
43 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
44 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
45 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
46 #define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
47 #define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */
58 #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
59 #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
60 #define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */
61 #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
62 #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
64 #define GREG_SWRST 0x1010UL /* Software Reset Register */
65 #define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */
66 #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */
67 #define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */
70 #define SUNGEM_MMIO_TXDMA_SIZE 0x1000
72 #define TXDMA_KICK 0x0000UL /* TX Kick Register */
74 #define TXDMA_CFG 0x0004UL /* TX Configuration Register */
75 #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
76 #define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */
78 #define TXDMA_DBLOW 0x0008UL /* TX Desc. Base Low */
79 #define TXDMA_DBHI 0x000CUL /* TX Desc. Base High */
80 #define TXDMA_PCNT 0x0024UL /* TX FIFO Packet Counter */
81 #define TXDMA_SMACHINE 0x0028UL /* TX State Machine Register */
82 #define TXDMA_DPLOW 0x0030UL /* TX Data Pointer Low */
83 #define TXDMA_DPHI 0x0034UL /* TX Data Pointer High */
84 #define TXDMA_TXDONE 0x0100UL /* TX Completion Register */
85 #define TXDMA_FTAG 0x0108UL /* TX FIFO Tag */
86 #define TXDMA_FSZ 0x0118UL /* TX FIFO Size */
89 #define SUNGEM_MMIO_RXDMA_SIZE 0x2000
91 #define RXDMA_CFG 0x0000UL /* RX Configuration Register */
92 #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
93 #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */
94 #define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */
95 #define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */
97 #define RXDMA_DBLOW 0x0004UL /* RX Descriptor Base Low */
98 #define RXDMA_DBHI 0x0008UL /* RX Descriptor Base High */
99 #define RXDMA_PCNT 0x0018UL /* RX FIFO Packet Counter */
100 #define RXDMA_SMACHINE 0x001CUL /* RX State Machine Register */
101 #define RXDMA_PTHRESH 0x0020UL /* Pause Thresholds */
102 #define RXDMA_DPLOW 0x0024UL /* RX Data Pointer Low */
103 #define RXDMA_DPHI 0x0028UL /* RX Data Pointer High */
104 #define RXDMA_KICK 0x0100UL /* RX Kick Register */
105 #define RXDMA_DONE 0x0104UL /* RX Completion Register */
106 #define RXDMA_BLANK 0x0108UL /* RX Blanking Register */
107 #define RXDMA_FTAG 0x0110UL /* RX FIFO Tag */
108 #define RXDMA_FSZ 0x0120UL /* RX FIFO Size */
111 #define SUNGEM_MMIO_WOL_SIZE 0x14
113 #define WOL_MATCH0 0x0000UL
114 #define WOL_MATCH1 0x0004UL
115 #define WOL_MATCH2 0x0008UL
116 #define WOL_MCOUNT 0x000CUL
117 #define WOL_WAKECSR 0x0010UL
120 #define SUNGEM_MMIO_MAC_SIZE 0x200
122 #define MAC_TXRST 0x0000UL /* TX MAC Software Reset Command */
123 #define MAC_RXRST 0x0004UL /* RX MAC Software Reset Command */
124 #define MAC_TXSTAT 0x0010UL /* TX MAC Status Register */
125 #define MAC_RXSTAT 0x0014UL /* RX MAC Status Register */
127 #define MAC_CSTAT 0x0018UL /* MAC Control Status Register */
128 #define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */
130 #define MAC_TXMASK 0x0020UL /* TX MAC Mask Register */
131 #define MAC_RXMASK 0x0024UL /* RX MAC Mask Register */
132 #define MAC_MCMASK 0x0028UL /* MAC Control Mask Register */
134 #define MAC_TXCFG 0x0030UL /* TX MAC Configuration Register */
135 #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
137 #define MAC_RXCFG 0x0034UL /* RX MAC Configuration Register */
138 #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
139 #define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */
140 #define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */
141 #define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */
142 #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
144 #define MAC_XIFCFG 0x003CUL /* XIF Configuration Register */
145 #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
147 #define MAC_MINFSZ 0x0050UL /* MinFrameSize Register */
148 #define MAC_MAXFSZ 0x0054UL /* MaxFrameSize Register */
149 #define MAC_ADDR0 0x0080UL /* MAC Address 0 Register */
150 #define MAC_ADDR1 0x0084UL /* MAC Address 1 Register */
151 #define MAC_ADDR2 0x0088UL /* MAC Address 2 Register */
152 #define MAC_ADDR3 0x008CUL /* MAC Address 3 Register */
153 #define MAC_ADDR4 0x0090UL /* MAC Address 4 Register */
154 #define MAC_ADDR5 0x0094UL /* MAC Address 5 Register */
155 #define MAC_HASH0 0x00C0UL /* Hash Table 0 Register */
156 #define MAC_PATMPS 0x0114UL /* Peak Attempts Register */
157 #define MAC_SMACHINE 0x0134UL /* State Machine Register */
160 #define SUNGEM_MMIO_MIF_SIZE 0x20
162 #define MIF_FRAME 0x000CUL /* MIF Frame/Output Register */
163 #define MIF_FRAME_OP 0x30000000 /* OPcode */
164 #define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */
165 #define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
166 #define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */
167 #define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */
169 #define MIF_CFG 0x0010UL /* MIF Configuration Register */
170 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
171 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
173 #define MIF_STATUS 0x0018UL /* MIF Status Register */
174 #define MIF_SMACHINE 0x001CUL /* MIF State Machine Register */
177 #define SUNGEM_MMIO_PCS_SIZE 0x60
178 #define PCS_MIISTAT 0x0004UL /* PCS MII Status Register */
179 #define PCS_ISTAT 0x0018UL /* PCS Interrupt Status Reg */
181 #define PCS_SSTATE 0x005CUL /* Serialink State Register */
189 #define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */
190 #define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */
191 #define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */
192 #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
193 #define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */
194 #define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */
195 #define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */
202 #define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */
203 #define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */
248 pci_set_irq(PCI_DEVICE(s), 0); in sungem_eval_irq()
339 s->tx_size = 0; in sungem_process_tx_desc()
369 s->tx_size = 0; in sungem_process_tx_desc()
370 s->tx_first_ctl = 0; in sungem_process_tx_desc()
458 if ((rxmac_cfg & MAC_RXCFG_ENAB) == 0) { in sungem_can_receive()
462 if ((rxdma_cfg & RXDMA_CFG_ENABLE) == 0) { in sungem_can_receive()
500 mac2 = (mac[0] << 8) | mac[1]; in sungem_check_rx_mac()
505 if (mac0 == 0xffff && mac1 == 0xffff && mac2 == 0xffff) { in sungem_check_rx_mac()
512 if (mac[0] & 1) { in sungem_check_rx_mac()
527 idx = (crc >> 2) & 0x3c; in sungem_check_rx_mac()
529 if (hash & (1 << (15 - (crc & 0xf)))) { in sungem_check_rx_mac()
572 max_fsize = s->macregs[MAC_MAXFSZ >> 2] & 0x7fff; in sungem_receive()
578 return 0; in sungem_receive()
583 fcs_size = 0; in sungem_receive()
617 return 0; in sungem_receive()
706 s->rxdmaregs[RXDMA_FSZ >> 2] = 0x140; in sungem_reset_rx()
707 s->rxdmaregs[RXDMA_DONE >> 2] = 0; in sungem_reset_rx()
708 s->rxdmaregs[RXDMA_KICK >> 2] = 0; in sungem_reset_rx()
709 s->rxdmaregs[RXDMA_CFG >> 2] = 0x1000010; in sungem_reset_rx()
710 s->rxdmaregs[RXDMA_PTHRESH >> 2] = 0xf8; in sungem_reset_rx()
711 s->rxdmaregs[RXDMA_BLANK >> 2] = 0; in sungem_reset_rx()
722 s->txdmaregs[TXDMA_FSZ >> 2] = 0x90; in sungem_reset_tx()
723 s->txdmaregs[TXDMA_TXDONE >> 2] = 0; in sungem_reset_tx()
724 s->txdmaregs[TXDMA_KICK >> 2] = 0; in sungem_reset_tx()
725 s->txdmaregs[TXDMA_CFG >> 2] = 0x118010; in sungem_reset_tx()
729 s->tx_size = 0; in sungem_reset_tx()
730 s->tx_first_ctl = 0; in sungem_reset_tx()
740 s->gregs[GREG_IMASK >> 2] = 0xFFFFFFF; in sungem_reset_all()
741 s->gregs[GREG_STAT >> 2] = 0; in sungem_reset_all()
745 s->gregs[GREG_SWRST >> 2] = 0; in sungem_reset_all()
748 s->macregs[MAC_ADDR2 >> 2] = (ma[0] << 8) | ma[1]; in sungem_reset_all()
767 return 0xffff; in __sungem_mii_read()
770 * ID is 0x00406210. TODO: Do a gigabit PHY like BCM5400 in __sungem_mii_read()
774 return 0; in __sungem_mii_read()
776 return 0x0040; in __sungem_mii_read()
778 return 0x6210; in __sungem_mii_read()
789 case 0x18: /* 5201 AUX status */ in __sungem_mii_read()
792 return 0; in __sungem_mii_read()
814 return 0xffff; in sungem_mii_op()
828 return 0xffff | MIF_FRAME_TALSB; in sungem_mii_op()
836 if (!(addr < 0x20) && !(addr >= 0x1000 && addr <= 0x1010)) { in sungem_mmio_greg_write()
838 "Write to unknown GREG register 0x%"HWADDR_PRIx"\n", in sungem_mmio_greg_write()
859 val &= 0x7; in sungem_mmio_greg_write()
891 if (!(addr < 0x20) && !(addr >= 0x1000 && addr <= 0x1010)) { in sungem_mmio_greg_read()
893 "Read from unknown GREG register 0x%"HWADDR_PRIx"\n", in sungem_mmio_greg_read()
895 return 0; in sungem_mmio_greg_read()
939 if (!(addr < 0x38) && !(addr >= 0x100 && addr <= 0x118)) { in sungem_mmio_txdma_write()
941 "Write to unknown TXDMA register 0x%"HWADDR_PRIx"\n", in sungem_mmio_txdma_write()
979 if (!(addr < 0x38) && !(addr >= 0x100 && addr <= 0x118)) { in sungem_mmio_txdma_read()
981 "Read from unknown TXDMA register 0x%"HWADDR_PRIx"\n", in sungem_mmio_txdma_read()
983 return 0; in sungem_mmio_txdma_read()
1008 if (!(addr <= 0x28) && !(addr >= 0x100 && addr <= 0x120)) { in sungem_mmio_rxdma_write()
1010 "Write to unknown RXDMA register 0x%"HWADDR_PRIx"\n", in sungem_mmio_rxdma_write()
1039 if ((s->macregs[MAC_RXCFG >> 2] & MAC_RXCFG_ENAB) != 0 && in sungem_mmio_rxdma_write()
1040 (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) { in sungem_mmio_rxdma_write()
1052 if (!(addr <= 0x28) && !(addr >= 0x100 && addr <= 0x120)) { in sungem_mmio_rxdma_read()
1054 "Read from unknown RXDMA register 0x%"HWADDR_PRIx"\n", in sungem_mmio_rxdma_read()
1056 return 0; in sungem_mmio_rxdma_read()
1083 if (val != 0) { in sungem_mmio_wol_write()
1118 if (!(addr <= 0x134)) { in sungem_mmio_mac_write()
1120 "Write to unknown MAC register 0x%"HWADDR_PRIx"\n", in sungem_mmio_mac_write()
1140 val &= 0x3ff; in sungem_mmio_mac_write()
1155 if ((s->macregs[MAC_RXCFG >> 2] & MAC_RXCFG_ENAB) != 0 && in sungem_mmio_mac_write()
1156 (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) { in sungem_mmio_mac_write()
1168 if (!(addr <= 0x134)) { in sungem_mmio_mac_read()
1170 "Read from unknown MAC register 0x%"HWADDR_PRIx"\n", in sungem_mmio_mac_read()
1172 return 0; in sungem_mmio_mac_read()
1182 s->macregs[addr >> 2] = 0; in sungem_mmio_mac_read()
1187 s->macregs[addr >> 2] = 0; in sungem_mmio_mac_read()
1215 if (!(addr <= 0x1c)) { in sungem_mmio_mif_write()
1217 "Write to unknown MIF register 0x%"HWADDR_PRIx"\n", in sungem_mmio_mif_write()
1252 if (!(addr <= 0x1c)) { in sungem_mmio_mif_read()
1254 "Read from unknown MIF register 0x%"HWADDR_PRIx"\n", in sungem_mmio_mif_read()
1256 return 0; in sungem_mmio_mif_read()
1281 if (!(addr <= 0x18) && !(addr >= 0x50 && addr <= 0x5c)) { in sungem_mmio_pcs_write()
1283 "Write to unknown PCS register 0x%"HWADDR_PRIx"\n", in sungem_mmio_pcs_write()
1307 if (!(addr <= 0x18) && !(addr >= 0x50 && addr <= 0x5c)) { in sungem_mmio_pcs_read()
1309 "Read from unknown PCS register 0x%"HWADDR_PRIx"\n", in sungem_mmio_pcs_read()
1311 return 0; in sungem_mmio_pcs_read()
1359 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); in sungem_realize()
1360 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); in sungem_realize()
1363 pci_conf[PCI_MIN_GNT] = 0x40; in sungem_realize()
1364 pci_conf[PCI_MAX_LAT] = 0x40; in sungem_realize()
1371 memory_region_add_subregion(&s->sungem, 0, &s->greg); in sungem_realize()
1375 memory_region_add_subregion(&s->sungem, 0x2000, &s->txdma); in sungem_realize()
1379 memory_region_add_subregion(&s->sungem, 0x4000, &s->rxdma); in sungem_realize()
1383 memory_region_add_subregion(&s->sungem, 0x3000, &s->wol); in sungem_realize()
1387 memory_region_add_subregion(&s->sungem, 0x6000, &s->mac); in sungem_realize()
1391 memory_region_add_subregion(&s->sungem, 0x6200, &s->mif); in sungem_realize()
1395 memory_region_add_subregion(&s->sungem, 0x9000, &s->pcs); in sungem_realize()
1397 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->sungem); in sungem_realize()
1419 "bootindex", "/ethernet-phy@0", in sungem_instance_init()
1425 /* Phy address should be 0 for most Apple machines except
1429 DEFINE_PROP_UINT32("phy_addr", SunGEMState, phy_addr, 0),
1434 .version_id = 0,
1435 .minimum_version_id = 0,
1466 k->revision = 0x01; in sungem_class_init()