Lines Matching +full:0 +full:x3000
20 * values below are offset by - 0x1000 from datasheet
21 * because its memory region is start at 0x1000
24 REG32(GICINT128_EN, 0x000)
25 REG32(GICINT128_STATUS, 0x004)
26 REG32(GICINT129_EN, 0x100)
27 REG32(GICINT129_STATUS, 0x104)
28 REG32(GICINT130_EN, 0x200)
29 REG32(GICINT130_STATUS, 0x204)
30 REG32(GICINT131_EN, 0x300)
31 REG32(GICINT131_STATUS, 0x304)
32 REG32(GICINT132_EN, 0x400)
33 REG32(GICINT132_STATUS, 0x404)
34 REG32(GICINT133_EN, 0x500)
35 REG32(GICINT133_STATUS, 0x504)
36 REG32(GICINT134_EN, 0x600)
37 REG32(GICINT134_STATUS, 0x604)
38 REG32(GICINT135_EN, 0x700)
39 REG32(GICINT135_STATUS, 0x704)
40 REG32(GICINT136_EN, 0x800)
41 REG32(GICINT136_STATUS, 0x804)
42 REG32(GICINT192_201_EN, 0xB00)
43 REG32(GICINT192_201_STATUS, 0xB04)
48 * values below are offset by - 0x100 from datasheet
49 * because its memory region is start at 0x100
52 REG32(GICINT192_EN, 0x00)
53 REG32(GICINT192_STATUS, 0x04)
54 REG32(GICINT193_EN, 0x10)
55 REG32(GICINT193_STATUS, 0x14)
56 REG32(GICINT194_EN, 0x20)
57 REG32(GICINT194_STATUS, 0x24)
58 REG32(GICINT195_EN, 0x30)
59 REG32(GICINT195_STATUS, 0x34)
60 REG32(GICINT196_EN, 0x40)
61 REG32(GICINT196_STATUS, 0x44)
62 REG32(GICINT197_EN, 0x50)
63 REG32(GICINT197_STATUS, 0x54)
68 REG32(SSPINT128_EN, 0x2000)
69 REG32(SSPINT128_STATUS, 0x2004)
70 REG32(SSPINT129_EN, 0x2100)
71 REG32(SSPINT129_STATUS, 0x2104)
72 REG32(SSPINT130_EN, 0x2200)
73 REG32(SSPINT130_STATUS, 0x2204)
74 REG32(SSPINT131_EN, 0x2300)
75 REG32(SSPINT131_STATUS, 0x2304)
76 REG32(SSPINT132_EN, 0x2400)
77 REG32(SSPINT132_STATUS, 0x2404)
78 REG32(SSPINT133_EN, 0x2500)
79 REG32(SSPINT133_STATUS, 0x2504)
80 REG32(SSPINT134_EN, 0x2600)
81 REG32(SSPINT134_STATUS, 0x2604)
82 REG32(SSPINT135_EN, 0x2700)
83 REG32(SSPINT135_STATUS, 0x2704)
84 REG32(SSPINT136_EN, 0x2800)
85 REG32(SSPINT136_STATUS, 0x2804)
86 REG32(SSPINT137_EN, 0x2900)
87 REG32(SSPINT137_STATUS, 0x2904)
88 REG32(SSPINT138_EN, 0x2A00)
89 REG32(SSPINT138_STATUS, 0x2A04)
90 REG32(SSPINT160_169_EN, 0x2B00)
91 REG32(SSPINT160_169_STATUS, 0x2B04)
96 REG32(SSPINT160_EN, 0x180)
97 REG32(SSPINT160_STATUS, 0x184)
98 REG32(SSPINT161_EN, 0x190)
99 REG32(SSPINT161_STATUS, 0x194)
100 REG32(SSPINT162_EN, 0x1A0)
101 REG32(SSPINT162_STATUS, 0x1A4)
102 REG32(SSPINT163_EN, 0x1B0)
103 REG32(SSPINT163_STATUS, 0x1B4)
104 REG32(SSPINT164_EN, 0x1C0)
105 REG32(SSPINT164_STATUS, 0x1C4)
106 REG32(SSPINT165_EN, 0x1D0)
107 REG32(SSPINT165_STATUS, 0x1D4)
112 REG32(TSPINT128_EN, 0x3000)
113 REG32(TSPINT128_STATUS, 0x3004)
114 REG32(TSPINT129_EN, 0x3100)
115 REG32(TSPINT129_STATUS, 0x3104)
116 REG32(TSPINT130_EN, 0x3200)
117 REG32(TSPINT130_STATUS, 0x3204)
118 REG32(TSPINT131_EN, 0x3300)
119 REG32(TSPINT131_STATUS, 0x3304)
120 REG32(TSPINT132_EN, 0x3400)
121 REG32(TSPINT132_STATUS, 0x3404)
122 REG32(TSPINT133_EN, 0x3500)
123 REG32(TSPINT133_STATUS, 0x3504)
124 REG32(TSPINT134_EN, 0x3600)
125 REG32(TSPINT134_STATUS, 0x3604)
126 REG32(TSPINT135_EN, 0x3700)
127 REG32(TSPINT135_STATUS, 0x3704)
128 REG32(TSPINT136_EN, 0x3800)
129 REG32(TSPINT136_STATUS, 0x3804)
130 REG32(TSPINT137_EN, 0x3900)
131 REG32(TSPINT137_STATUS, 0x3904)
132 REG32(TSPINT138_EN, 0x3A00)
133 REG32(TSPINT138_STATUS, 0x3A04)
134 REG32(TSPINT160_169_EN, 0x3B00)
135 REG32(TSPINT160_169_STATUS, 0x3B04)
141 REG32(TSPINT160_EN, 0x200)
142 REG32(TSPINT160_STATUS, 0x204)
143 REG32(TSPINT161_EN, 0x210)
144 REG32(TSPINT161_STATUS, 0x214)
145 REG32(TSPINT162_EN, 0x220)
146 REG32(TSPINT162_STATUS, 0x224)
147 REG32(TSPINT163_EN, 0x230)
148 REG32(TSPINT163_STATUS, 0x234)
149 REG32(TSPINT164_EN, 0x240)
150 REG32(TSPINT164_STATUS, 0x244)
151 REG32(TSPINT165_EN, 0x250)
152 REG32(TSPINT165_STATUS, 0x254)
159 for (i = 0; i < aic->irq_table_count; i++) { in aspeed_intc_get_irq()
175 * The input pin index should be between 0 and the number of input pins.
176 * The output pin index should be between 0 and the number of output pins.
205 * a. mask is not 0 means in ISR mode in aspeed_intc_set_irq_handler()
207 * b. status register value is not 0 means previous in aspeed_intc_set_irq_handler()
241 for (i = 0; i < num_outpins; i++) { in aspeed_intc_set_irq_handler_multi_outpins()
246 * a. mask bit is not 0 means in ISR mode sources interrupt in aspeed_intc_set_irq_handler_multi_outpins()
248 * b. status bit is not 0 means previous source interrupt in aspeed_intc_set_irq_handler_multi_outpins()
271 * GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9.
273 * IRQs 10 to 18. The value of input IRQ should be between 0 and
282 uint32_t select = 0; in aspeed_intc_set_irq()
300 for (i = 0; i < aic->num_lines; i++) { in aspeed_intc_set_irq()
382 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__); in aspeed_intc_status_handler()
401 if (data == 0xffffffff) { in aspeed_intc_status_handler()
415 s->pending[inpin_idx] = 0; in aspeed_intc_status_handler()
421 trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx, 0); in aspeed_intc_status_handler()
422 aspeed_intc_update(s, inpin_idx, outpin_idx, 0); in aspeed_intc_status_handler()
440 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__); in aspeed_intc_status_handler_multi_outpins()
459 if (data == 0xffffffff) { in aspeed_intc_status_handler_multi_outpins()
463 for (i = 0; i < num_outpins; i++) { in aspeed_intc_status_handler_multi_outpins()
480 trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx + i, 0); in aspeed_intc_status_handler_multi_outpins()
481 aspeed_intc_update(s, inpin_idx, outpin_idx + i, 0); in aspeed_intc_status_handler_multi_outpins()
492 uint32_t value = 0; in aspeed_intc_read()
632 uint32_t value = 0; in aspeed_intcio_read()
809 for (i = 0; i < aic->num_inpins; i++) { in aspeed_intc_instance_init()
822 memset(s->regs, 0, aic->nr_regs << 2); in aspeed_intc_reset()
823 memset(s->enable, 0, sizeof(s->enable)); in aspeed_intc_reset()
824 memset(s->mask, 0, sizeof(s->mask)); in aspeed_intc_reset()
825 memset(s->pending, 0, sizeof(s->pending)); in aspeed_intc_reset()
849 for (i = 0; i < aic->num_inpins; i++) { in aspeed_intc_realize()
855 for (i = 0; i < aic->num_outpins; i++) { in aspeed_intc_realize()
893 {0, 0, 10, R_GICINT192_201_EN, R_GICINT192_201_STATUS},
914 aic->mem_size = 0x4000; in aspeed_2700_intc_class_init()
915 aic->nr_regs = 0xB08 >> 2; in aspeed_2700_intc_class_init()
916 aic->reg_offset = 0x1000; in aspeed_2700_intc_class_init()
928 {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
945 aic->mem_size = 0x400; in aspeed_2700_intcio_class_init()
946 aic->nr_regs = 0x58 >> 2; in aspeed_2700_intcio_class_init()
947 aic->reg_offset = 0x100; in aspeed_2700_intcio_class_init()
960 {0, 0, 10, R_SSPINT160_169_EN, R_SSPINT160_169_STATUS},
981 aic->mem_size = 0x4000; in aspeed_2700ssp_intc_class_init()
982 aic->nr_regs = 0x2B08 >> 2; in aspeed_2700ssp_intc_class_init()
983 aic->reg_offset = 0x0; in aspeed_2700ssp_intc_class_init()
996 {0, 0, 1, R_SSPINT160_EN, R_SSPINT160_STATUS},
1014 aic->mem_size = 0x400; in aspeed_2700ssp_intcio_class_init()
1015 aic->nr_regs = 0x1d8 >> 2; in aspeed_2700ssp_intcio_class_init()
1016 aic->reg_offset = 0; in aspeed_2700ssp_intcio_class_init()
1029 {0, 0, 10, R_TSPINT160_169_EN, R_TSPINT160_169_STATUS},
1050 aic->mem_size = 0x4000; in aspeed_2700tsp_intc_class_init()
1051 aic->nr_regs = 0x3B08 >> 2; in aspeed_2700tsp_intc_class_init()
1052 aic->reg_offset = 0; in aspeed_2700tsp_intc_class_init()
1065 {0, 0, 1, R_TSPINT160_EN, R_TSPINT160_STATUS},
1083 aic->mem_size = 0x400; in aspeed_2700tsp_intcio_class_init()
1084 aic->nr_regs = 0x258 >> 2; in aspeed_2700tsp_intcio_class_init()
1085 aic->reg_offset = 0x0; in aspeed_2700tsp_intcio_class_init()