Lines Matching +full:0 +full:x3000
127 #define TIMEOUT_INTR (1 << 0)
154 a->src = ch->addr[0]; in omap_dma_channel_load()
159 a->frame = 0; in omap_dma_channel_load()
160 a->element = 0; in omap_dma_channel_load()
161 a->pck_element = 0; in omap_dma_channel_load()
168 for (i = 0; i < 2; i ++) in omap_dma_channel_load()
171 a->elem_delta[i] = 0; in omap_dma_channel_load()
172 a->frame_delta[i] = 0; in omap_dma_channel_load()
176 a->frame_delta[i] = 0; in omap_dma_channel_load()
180 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
181 a->frame_delta[i] = 0; in omap_dma_channel_load()
185 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
186 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - in omap_dma_channel_load()
187 ch->element_index[omap_3_1 ? 0 : i]; in omap_dma_channel_load()
196 (ch->endian[0] | ch->endian_lock[0]) == in omap_dma_channel_load()
198 for (i = 0; i < 2; i ++) { in omap_dma_channel_load()
199 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just in omap_dma_channel_load()
228 ch->set_update = 0; in omap_dma_activate_channel()
242 ch->cpc = ch->active_set.dest & 0xffff; in omap_dma_deactivate_channel()
246 ch->pending_request = 0; in omap_dma_deactivate_channel()
256 ch->active = 0; in omap_dma_deactivate_channel()
258 soc_dma_set_request(ch->dma, 0); in omap_dma_deactivate_channel()
267 ch->waiting_end_prog = 0; in omap_dma_enable_channel()
282 ch->enable = 0; in omap_dma_disable_channel()
284 ch->pending_request = 0; in omap_dma_disable_channel()
293 ch->waiting_end_prog = 0; in omap_dma_channel_end_prog()
295 ch->pending_request = 0; in omap_dma_channel_end_prog()
306 if (ch[0].status | ch[6].status) in omap_dma_interrupts_3_1_update()
307 qemu_irq_raise(ch[0].irq); in omap_dma_interrupts_3_1_update()
332 s->omap_3_1_mapping_disabled = 0; in omap_dma_enable_3_1_mapping()
347 int drop_event = 0; in omap_dma_process_request()
350 for (channel = 0; channel < s->chans; channel ++, ch ++) { in omap_dma_process_request()
390 a->src += a->elem_delta[0]; in omap_dma_transfer_generic()
397 a->element = 0; in omap_dma_transfer_generic()
398 a->src += a->frame_delta[0]; in omap_dma_transfer_generic()
404 ch->cpc = a->dest & 0xffff; in omap_dma_transfer_generic()
427 a->pck_element = 0; in omap_dma_transfer_generic()
441 a->element = 0; in omap_dma_transfer_generic()
442 a->src += a->frame_delta[0]; in omap_dma_transfer_generic()
452 ch->cpc = a->dest & 0xffff; in omap_dma_transfer_generic()
510 src_p = &s->mpu->port[ch->port[0]];
514 #if 0
558 (a->element >= (a->elements >> 1) ? a->elements : 0) -
665 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
670 ch->cpc = a->dest & 0xffff;
689 s->gcr = 0x0004;
690 s->ocp = 0x00000000;
691 memset(&s->irqstat, 0, sizeof(s->irqstat));
692 memset(&s->irqen, 0, sizeof(s->irqen));
694 s->lcd_ch.condition = 0;
695 s->lcd_ch.interrupts = 0;
696 s->lcd_ch.dual = 0;
698 for (i = 0; i < s->chans; i ++) {
699 s->ch[i].suspend = 0;
700 s->ch[i].prefetch = 0;
701 s->ch[i].buf_disable = 0;
702 s->ch[i].src_sync = 0;
703 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
704 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
705 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
706 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
707 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
708 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
709 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
710 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
711 s->ch[i].write_mode = 0;
712 s->ch[i].data_type = 0;
713 s->ch[i].transparent_copy = 0;
714 s->ch[i].constant_fill = 0;
715 s->ch[i].color = 0x00000000;
716 s->ch[i].end_prog = 0;
717 s->ch[i].repeat = 0;
718 s->ch[i].auto_init = 0;
719 s->ch[i].link_enabled = 0;
720 s->ch[i].interrupts = 0x0003;
721 s->ch[i].status = 0;
722 s->ch[i].cstatus = 0;
723 s->ch[i].active = 0;
724 s->ch[i].enable = 0;
725 s->ch[i].sync = 0;
726 s->ch[i].pending_request = 0;
727 s->ch[i].waiting_end_prog = 0;
728 s->ch[i].cpc = 0x0000;
729 s->ch[i].fs = 0;
730 s->ch[i].bs = 0;
731 s->ch[i].omap_3_1_compatible_disable = 0;
732 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
733 s->ch[i].priority = 0;
734 s->ch[i].interleave_disabled = 0;
735 s->ch[i].type = 0;
743 case 0x00: /* SYS_DMA_CSDP_CH0 */
747 (ch->burst[0] << 7) |
748 (ch->pack[0] << 6) |
749 (ch->port[0] << 2) |
753 case 0x02: /* SYS_DMA_CCR_CH0 */
755 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
759 (ch->mode[0] << 12) |
768 case 0x04: /* SYS_DMA_CICR_CH0 */
772 case 0x06: /* SYS_DMA_CSR_CH0 */
776 *value |= (ch->sibling->status & 0x3f) << 6;
782 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
783 *value = ch->addr[0] & 0x0000ffff;
786 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
787 *value = ch->addr[0] >> 16;
790 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
791 *value = ch->addr[1] & 0x0000ffff;
794 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
798 case 0x10: /* SYS_DMA_CEN_CH0 */
802 case 0x12: /* SYS_DMA_CFN_CH0 */
806 case 0x14: /* SYS_DMA_CFI_CH0 */
807 *value = ch->frame_index[0];
810 case 0x16: /* SYS_DMA_CEI_CH0 */
811 *value = ch->element_index[0];
814 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
816 *value = ch->active_set.src & 0xffff; /* CSAC */
821 case 0x1a: /* DMA_CDAC */
822 *value = ch->active_set.dest & 0xffff; /* CDAC */
825 case 0x1c: /* DMA_CDEI */
829 case 0x1e: /* DMA_CDFI */
833 case 0x20: /* DMA_COLOR_L */
834 *value = ch->color & 0xffff;
837 case 0x22: /* DMA_COLOR_U */
841 case 0x24: /* DMA_CCR2 */
847 case 0x28: /* DMA_CLNK_CTRL */
849 (ch->link_next_ch & 0xf);
852 case 0x2a: /* DMA_LCH_CTRL */
860 return 0;
867 case 0x00: /* SYS_DMA_CSDP_CH0 */
868 ch->burst[1] = (value & 0xc000) >> 14;
869 ch->pack[1] = (value & 0x2000) >> 13;
870 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
871 ch->burst[0] = (value & 0x0180) >> 7;
872 ch->pack[0] = (value & 0x0040) >> 6;
873 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
874 if (ch->port[0] >= __omap_dma_port_last) {
876 __func__, ch->port[0]);
890 case 0x02: /* SYS_DMA_CCR_CH0 */
891 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
892 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
893 ch->end_prog = (value & 0x0800) >> 11;
895 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
896 ch->repeat = (value & 0x0200) >> 9;
897 ch->auto_init = (value & 0x0100) >> 8;
898 ch->priority = (value & 0x0040) >> 6;
899 ch->fs = (value & 0x0020) >> 5;
900 ch->sync = value & 0x001f;
902 if (value & 0x0080)
912 case 0x04: /* SYS_DMA_CICR_CH0 */
913 ch->interrupts = value & 0x3f;
916 case 0x06: /* SYS_DMA_CSR_CH0 */
920 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
921 ch->addr[0] &= 0xffff0000;
922 ch->addr[0] |= value;
925 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
926 ch->addr[0] &= 0x0000ffff;
927 ch->addr[0] |= (uint32_t) value << 16;
930 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
931 ch->addr[1] &= 0xffff0000;
935 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
936 ch->addr[1] &= 0x0000ffff;
940 case 0x10: /* SYS_DMA_CEN_CH0 */
944 case 0x12: /* SYS_DMA_CFN_CH0 */
948 case 0x14: /* SYS_DMA_CFI_CH0 */
949 ch->frame_index[0] = (int16_t) value;
952 case 0x16: /* SYS_DMA_CEI_CH0 */
953 ch->element_index[0] = (int16_t) value;
956 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
960 case 0x1c: /* DMA_CDEI */
964 case 0x1e: /* DMA_CDFI */
968 case 0x20: /* DMA_COLOR_L */
969 ch->color &= 0xffff0000;
973 case 0x22: /* DMA_COLOR_U */
974 ch->color &= 0xffff;
978 case 0x24: /* DMA_CCR2 */
979 ch->bs = (value >> 2) & 0x1;
980 ch->transparent_copy = (value >> 1) & 0x1;
981 ch->constant_fill = value & 0x1;
984 case 0x28: /* DMA_CLNK_CTRL */
985 ch->link_enabled = (value >> 15) & 0x1;
987 ch->link_enabled = 0;
990 ch->link_next_ch = value & 0x1f;
993 case 0x2a: /* DMA_LCH_CTRL */
994 ch->interleave_disabled = (value >> 15) & 0x1;
995 ch->type = value & 0xf;
1001 return 0;
1008 case 0xbc0: /* DMA_LCD_CSDP */
1009 s->brust_f2 = (value >> 14) & 0x3;
1010 s->pack_f2 = (value >> 13) & 0x1;
1011 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1012 s->brust_f1 = (value >> 7) & 0x3;
1013 s->pack_f1 = (value >> 6) & 0x1;
1014 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1017 case 0xbc2: /* DMA_LCD_CCR */
1018 s->mode_f2 = (value >> 14) & 0x3;
1019 s->mode_f1 = (value >> 12) & 0x3;
1020 s->end_prog = (value >> 11) & 0x1;
1021 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1022 s->repeat = (value >> 9) & 0x1;
1023 s->auto_init = (value >> 8) & 0x1;
1024 s->running = (value >> 7) & 0x1;
1025 s->priority = (value >> 6) & 0x1;
1026 s->bs = (value >> 4) & 0x1;
1029 case 0xbc4: /* DMA_LCD_CTRL */
1030 s->dst = (value >> 8) & 0x1;
1031 s->src = ((value >> 6) & 0x3) << 1;
1032 s->condition = 0;
1038 case 0xbc8: /* TOP_B1_L */
1039 s->src_f1_top &= 0xffff0000;
1040 s->src_f1_top |= 0x0000ffff & value;
1043 case 0xbca: /* TOP_B1_U */
1044 s->src_f1_top &= 0x0000ffff;
1048 case 0xbcc: /* BOT_B1_L */
1049 s->src_f1_bottom &= 0xffff0000;
1050 s->src_f1_bottom |= 0x0000ffff & value;
1053 case 0xbce: /* BOT_B1_U */
1054 s->src_f1_bottom &= 0x0000ffff;
1058 case 0xbd0: /* TOP_B2_L */
1059 s->src_f2_top &= 0xffff0000;
1060 s->src_f2_top |= 0x0000ffff & value;
1063 case 0xbd2: /* TOP_B2_U */
1064 s->src_f2_top &= 0x0000ffff;
1068 case 0xbd4: /* BOT_B2_L */
1069 s->src_f2_bottom &= 0xffff0000;
1070 s->src_f2_bottom |= 0x0000ffff & value;
1073 case 0xbd6: /* BOT_B2_U */
1074 s->src_f2_bottom &= 0x0000ffff;
1078 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1082 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1083 s->frame_index_f1 &= 0xffff0000;
1084 s->frame_index_f1 |= 0x0000ffff & value;
1087 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1088 s->frame_index_f1 &= 0x0000ffff;
1092 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1096 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1097 s->frame_index_f2 &= 0xffff0000;
1098 s->frame_index_f2 |= 0x0000ffff & value;
1101 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1102 s->frame_index_f2 &= 0x0000ffff;
1106 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1110 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1114 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1118 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1122 case 0xbea: /* DMA_LCD_LCH_CTRL */
1123 s->lch_type = value & 0xf;
1129 return 0;
1136 case 0xbc0: /* DMA_LCD_CSDP */
1142 ((s->data_type_f1 >> 1) << 0);
1145 case 0xbc2: /* DMA_LCD_CCR */
1157 case 0xbc4: /* DMA_LCD_CTRL */
1160 ((s->src & 0x6) << 5) |
1166 case 0xbc8: /* TOP_B1_L */
1167 *ret = s->src_f1_top & 0xffff;
1170 case 0xbca: /* TOP_B1_U */
1174 case 0xbcc: /* BOT_B1_L */
1175 *ret = s->src_f1_bottom & 0xffff;
1178 case 0xbce: /* BOT_B1_U */
1182 case 0xbd0: /* TOP_B2_L */
1183 *ret = s->src_f2_top & 0xffff;
1186 case 0xbd2: /* TOP_B2_U */
1190 case 0xbd4: /* BOT_B2_L */
1191 *ret = s->src_f2_bottom & 0xffff;
1194 case 0xbd6: /* BOT_B2_U */
1198 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1202 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1203 *ret = s->frame_index_f1 & 0xffff;
1206 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1210 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1214 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1215 *ret = s->frame_index_f2 & 0xffff;
1218 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1222 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1226 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1230 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1234 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1238 case 0xbea: /* DMA_LCD_LCH_CTRL */
1245 return 0;
1252 case 0x300: /* SYS_DMA_LCD_CTRL */
1253 s->src = (value & 0x40) ? imif : emiff;
1254 s->condition = 0;
1260 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1261 s->src_f1_top &= 0xffff0000;
1262 s->src_f1_top |= 0x0000ffff & value;
1265 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1266 s->src_f1_top &= 0x0000ffff;
1270 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1271 s->src_f1_bottom &= 0xffff0000;
1272 s->src_f1_bottom |= 0x0000ffff & value;
1275 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1276 s->src_f1_bottom &= 0x0000ffff;
1280 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1281 s->src_f2_top &= 0xffff0000;
1282 s->src_f2_top |= 0x0000ffff & value;
1285 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1286 s->src_f2_top &= 0x0000ffff;
1290 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1291 s->src_f2_bottom &= 0xffff0000;
1292 s->src_f2_bottom |= 0x0000ffff & value;
1295 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1296 s->src_f2_bottom &= 0x0000ffff;
1303 return 0;
1312 case 0x300: /* SYS_DMA_LCD_CTRL */
1314 s->condition = 0;
1320 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1321 *ret = s->src_f1_top & 0xffff;
1324 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1328 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1329 *ret = s->src_f1_bottom & 0xffff;
1332 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1336 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1337 *ret = s->src_f2_top & 0xffff;
1340 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1344 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1345 *ret = s->src_f2_bottom & 0xffff;
1348 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1355 return 0;
1361 case 0x400: /* SYS_DMA_GCR */
1365 case 0x404: /* DMA_GSCR */
1366 if (value & 0x8)
1372 case 0x408: /* DMA_GRST */
1373 if (value & 0x1)
1380 return 0;
1387 case 0x400: /* SYS_DMA_GCR */
1391 case 0x404: /* DMA_GSCR */
1395 case 0x408: /* DMA_GRST */
1396 *ret = 0;
1399 case 0x442: /* DMA_HW_ID */
1400 case 0x444: /* DMA_PCh2_ID */
1401 case 0x446: /* DMA_PCh0_ID */
1402 case 0x448: /* DMA_PCh1_ID */
1403 case 0x44a: /* DMA_PChG_ID */
1404 case 0x44c: /* DMA_PChD_ID */
1408 case 0x44e: /* DMA_CAPS_0_U */
1409 *ret = (s->caps[0] >> 16) & 0xffff;
1411 case 0x450: /* DMA_CAPS_0_L */
1412 *ret = (s->caps[0] >> 0) & 0xffff;
1415 case 0x452: /* DMA_CAPS_1_U */
1416 *ret = (s->caps[1] >> 16) & 0xffff;
1418 case 0x454: /* DMA_CAPS_1_L */
1419 *ret = (s->caps[1] >> 0) & 0xffff;
1422 case 0x456: /* DMA_CAPS_2 */
1426 case 0x458: /* DMA_CAPS_3 */
1430 case 0x45a: /* DMA_CAPS_4 */
1434 case 0x460: /* DMA_PCh2_SR */
1435 case 0x480: /* DMA_PCh0_SR */
1436 case 0x482: /* DMA_PCh1_SR */
1437 case 0x4c0: /* DMA_PChD_SR_0 */
1441 *ret = 0xff;
1447 return 0;
1461 case 0x300 ... 0x3fe:
1468 case 0x000 ... 0x2fe:
1469 reg = addr & 0x3f;
1470 ch = (addr >> 6) & 0x0f;
1475 case 0x404 ... 0x4fe:
1479 case 0x400:
1484 case 0xb00 ... 0xbfe:
1494 return 0;
1509 case 0x300 ... 0x3fe:
1516 case 0x000 ... 0x2fe:
1517 reg = addr & 0x3f;
1518 ch = (addr >> 6) & 0x0f;
1523 case 0x404 ... 0x4fe:
1527 case 0x400:
1532 case 0xb00 ... 0xbfe:
1571 for (i = 0; i < s->chans; i ++)
1584 s->caps[0] =
1598 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1607 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1616 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1631 memsize = 0x800;
1634 memsize = 0xc00;
1651 for (i = 0; i < 3; i ++) {
1655 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1661 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));
1663 omap_dma_clk_update(s, 0, 1);