Lines Matching +full:0 +full:x3000
98 for (i = 0; i < 24; i++) { in sh4_translate_init()
154 for (i = 0; i < 32; i++) in sh4_translate_init()
165 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
167 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
169 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
171 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
172 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
177 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
180 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
183 qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
223 return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0; in use_exit_tb()
243 tcg_gen_exit_tb(NULL, 0); in gen_goto_tb()
259 tcg_gen_exit_tb(NULL, 0); in gen_jump()
265 gen_goto_tb(ctx, 0, ctx->delayed_pc); in gen_jump()
280 tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); in gen_conditional_jump()
284 gen_goto_tb(ctx, 0, dest); in gen_conditional_jump()
291 tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); in gen_conditional_jump()
292 gen_goto_tb(ctx, 0, dest); in gen_conditional_jump()
311 tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1); in gen_delayed_conditional_jump()
322 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1); in gen_delayed_conditional_jump()
331 tcg_debug_assert((reg & 1) == 0); in gen_load_fpr64()
339 tcg_debug_assert((reg & 1) == 0); in gen_store_fpr64()
344 #define B3_0 (ctx->opcode & 0xf)
345 #define B6_4 ((ctx->opcode >> 4) & 0x7)
346 #define B7_4 ((ctx->opcode >> 4) & 0xf)
347 #define B7_0 (ctx->opcode & 0xff)
348 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
349 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
350 (ctx->opcode & 0xfff))
351 #define B11_8 ((ctx->opcode >> 8) & 0xf)
352 #define B15_12 ((ctx->opcode >> 12) & 0xf)
355 #define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
358 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
414 int opcode = ctx->opcode & 0xf0ff; in _decode_opc()
415 if (opcode != 0x0093 /* ocbi */ in _decode_opc()
416 && opcode != 0x00c3 /* movca.l */) in _decode_opc()
419 ctx->has_movcal = 0; in _decode_opc()
423 #if 0 in _decode_opc()
424 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); in _decode_opc()
428 case 0x0019: /* div0u */ in _decode_opc()
429 tcg_gen_movi_i32(cpu_sr_m, 0); in _decode_opc()
430 tcg_gen_movi_i32(cpu_sr_q, 0); in _decode_opc()
431 tcg_gen_movi_i32(cpu_sr_t, 0); in _decode_opc()
433 case 0x000b: /* rts */ in _decode_opc()
439 case 0x0028: /* clrmac */ in _decode_opc()
440 tcg_gen_movi_i32(cpu_mach, 0); in _decode_opc()
441 tcg_gen_movi_i32(cpu_macl, 0); in _decode_opc()
443 case 0x0048: /* clrs */ in _decode_opc()
446 case 0x0008: /* clrt */ in _decode_opc()
447 tcg_gen_movi_i32(cpu_sr_t, 0); in _decode_opc()
449 case 0x0038: /* ldtlb */ in _decode_opc()
453 case 0x002b: /* rte */ in _decode_opc()
462 case 0x0058: /* sets */ in _decode_opc()
465 case 0x0018: /* sett */ in _decode_opc()
468 case 0xfbfd: /* frchg */ in _decode_opc()
473 case 0xf3fd: /* fschg */ in _decode_opc()
478 case 0xf7fd: /* fpchg */ in _decode_opc()
483 case 0x0009: /* nop */ in _decode_opc()
485 case 0x001b: /* sleep */ in _decode_opc()
492 switch (ctx->opcode & 0xf000) { in _decode_opc()
493 case 0x1000: /* mov.l Rm,@(disp,Rn) */ in _decode_opc()
501 case 0x5000: /* mov.l @(disp,Rm),Rn */ in _decode_opc()
509 case 0xe000: /* mov #imm,Rn */ in _decode_opc()
516 if (B11_8 == 15 && B7_0s < 0 && in _decode_opc()
525 case 0x9000: /* mov.w @(disp,PC),Rn */ in _decode_opc()
533 case 0xd000: /* mov.l @(disp,PC),Rn */ in _decode_opc()
541 case 0x7000: /* add #imm,Rn */ in _decode_opc()
544 case 0xa000: /* bra disp */ in _decode_opc()
549 case 0xb000: /* bsr disp */ in _decode_opc()
557 switch (ctx->opcode & 0xf00f) { in _decode_opc()
558 case 0x6003: /* mov Rm,Rn */ in _decode_opc()
561 case 0x2000: /* mov.b Rm,@Rn */ in _decode_opc()
564 case 0x2001: /* mov.w Rm,@Rn */ in _decode_opc()
568 case 0x2002: /* mov.l Rm,@Rn */ in _decode_opc()
572 case 0x6000: /* mov.b @Rm,Rn */ in _decode_opc()
575 case 0x6001: /* mov.w @Rm,Rn */ in _decode_opc()
579 case 0x6002: /* mov.l @Rm,Rn */ in _decode_opc()
583 case 0x2004: /* mov.b Rm,@-Rn */ in _decode_opc()
592 case 0x2005: /* mov.w Rm,@-Rn */ in _decode_opc()
601 case 0x2006: /* mov.l Rm,@-Rn */ in _decode_opc()
610 case 0x6004: /* mov.b @Rm+,Rn */ in _decode_opc()
615 case 0x6005: /* mov.w @Rm+,Rn */ in _decode_opc()
621 case 0x6006: /* mov.l @Rm+,Rn */ in _decode_opc()
627 case 0x0004: /* mov.b Rm,@(R0,Rn) */ in _decode_opc()
630 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
634 case 0x0005: /* mov.w Rm,@(R0,Rn) */ in _decode_opc()
637 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
642 case 0x0006: /* mov.l Rm,@(R0,Rn) */ in _decode_opc()
645 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
650 case 0x000c: /* mov.b @(R0,Rm),Rn */ in _decode_opc()
653 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
657 case 0x000d: /* mov.w @(R0,Rm),Rn */ in _decode_opc()
660 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
665 case 0x000e: /* mov.l @(R0,Rm),Rn */ in _decode_opc()
668 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
673 case 0x6008: /* swap.b Rm,Rn */ in _decode_opc()
676 tcg_gen_bswap16_i32(low, REG(B7_4), 0); in _decode_opc()
677 tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16); in _decode_opc()
680 case 0x6009: /* swap.w Rm,Rn */ in _decode_opc()
683 case 0x200d: /* xtrct Rm,Rn */ in _decode_opc()
693 case 0x300c: /* add Rm,Rn */ in _decode_opc()
696 case 0x300e: /* addc Rm,Rn */ in _decode_opc()
700 case 0x300f: /* addv Rm,Rn */ in _decode_opc()
718 case 0x2009: /* and Rm,Rn */ in _decode_opc()
721 case 0x3000: /* cmp/eq Rm,Rn */ in _decode_opc()
724 case 0x3003: /* cmp/ge Rm,Rn */ in _decode_opc()
727 case 0x3007: /* cmp/gt Rm,Rn */ in _decode_opc()
730 case 0x3006: /* cmp/hi Rm,Rn */ in _decode_opc()
733 case 0x3002: /* cmp/hs Rm,Rn */ in _decode_opc()
736 case 0x200c: /* cmp/str Rm,Rn */ in _decode_opc()
741 tcg_gen_subi_i32(cmp1, cmp2, 0x01010101); in _decode_opc()
743 tcg_gen_andi_i32(cmp1, cmp1, 0x80808080); in _decode_opc()
744 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_t, cmp1, 0); in _decode_opc()
747 case 0x2007: /* div0s Rm,Rn */ in _decode_opc()
752 case 0x3004: /* div1 Rm,Rn */ in _decode_opc()
757 TCGv zero = tcg_constant_i32(0); in _decode_opc()
767 that it is 0x00000000 when adding the value or 0xffffffff when in _decode_opc()
782 case 0x300d: /* dmuls.l Rm,Rn */ in _decode_opc()
785 case 0x3005: /* dmulu.l Rm,Rn */ in _decode_opc()
788 case 0x600e: /* exts.b Rm,Rn */ in _decode_opc()
791 case 0x600f: /* exts.w Rm,Rn */ in _decode_opc()
794 case 0x600c: /* extu.b Rm,Rn */ in _decode_opc()
797 case 0x600d: /* extu.w Rm,Rn */ in _decode_opc()
800 case 0x000f: /* mac.l @Rm+,@Rn+ */ in _decode_opc()
814 case 0x400f: /* mac.w @Rm+,@Rn+ */ in _decode_opc()
828 case 0x0007: /* mul.l Rm,Rn */ in _decode_opc()
831 case 0x200f: /* muls.w Rm,Rn */ in _decode_opc()
841 case 0x200e: /* mulu.w Rm,Rn */ in _decode_opc()
851 case 0x600b: /* neg Rm,Rn */ in _decode_opc()
854 case 0x600a: /* negc Rm,Rn */ in _decode_opc()
856 TCGv t0 = tcg_constant_i32(0); in _decode_opc()
864 case 0x6007: /* not Rm,Rn */ in _decode_opc()
867 case 0x200b: /* or Rm,Rn */ in _decode_opc()
870 case 0x400c: /* shad Rm,Rn */ in _decode_opc()
876 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc()
883 tcg_gen_xori_i32(t0, t0, 0x1f); in _decode_opc()
888 tcg_gen_movi_i32(t0, 0); in _decode_opc()
892 case 0x400d: /* shld Rm,Rn */ in _decode_opc()
898 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc()
905 tcg_gen_xori_i32(t0, t0, 0x1f); in _decode_opc()
910 tcg_gen_movi_i32(t0, 0); in _decode_opc()
914 case 0x3008: /* sub Rm,Rn */ in _decode_opc()
917 case 0x300a: /* subc Rm,Rn */ in _decode_opc()
920 t0 = tcg_constant_tl(0); in _decode_opc()
928 case 0x300b: /* subv Rm,Rn */ in _decode_opc()
946 case 0x2008: /* tst Rm,Rn */ in _decode_opc()
950 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
953 case 0x200a: /* xor Rm,Rn */ in _decode_opc()
956 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
967 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ in _decode_opc()
979 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
991 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
1005 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ in _decode_opc()
1023 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ in _decode_opc()
1027 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
1039 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ in _decode_opc()
1043 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
1055 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1056 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1057 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1058 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1059 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1060 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1066 if (ctx->opcode & 0x0110) { in _decode_opc()
1073 switch (ctx->opcode & 0xf00f) { in _decode_opc()
1074 case 0xf000: /* fadd Rm,Rn */ in _decode_opc()
1077 case 0xf001: /* fsub Rm,Rn */ in _decode_opc()
1080 case 0xf002: /* fmul Rm,Rn */ in _decode_opc()
1083 case 0xf003: /* fdiv Rm,Rn */ in _decode_opc()
1086 case 0xf004: /* fcmp/eq Rm,Rn */ in _decode_opc()
1089 case 0xf005: /* fcmp/gt Rm,Rn */ in _decode_opc()
1095 switch (ctx->opcode & 0xf00f) { in _decode_opc()
1096 case 0xf000: /* fadd Rm,Rn */ in _decode_opc()
1100 case 0xf001: /* fsub Rm,Rn */ in _decode_opc()
1104 case 0xf002: /* fmul Rm,Rn */ in _decode_opc()
1108 case 0xf003: /* fdiv Rm,Rn */ in _decode_opc()
1112 case 0xf004: /* fcmp/eq Rm,Rn */ in _decode_opc()
1116 case 0xf005: /* fcmp/gt Rm,Rn */ in _decode_opc()
1124 case 0xf00e: /* fmac FR0,RM,Rn */ in _decode_opc()
1128 FREG(0), FREG(B7_4), FREG(B11_8)); in _decode_opc()
1132 switch (ctx->opcode & 0xff00) { in _decode_opc()
1133 case 0xc900: /* and #imm,R0 */ in _decode_opc()
1134 tcg_gen_andi_i32(REG(0), REG(0), B7_0); in _decode_opc()
1136 case 0xcd00: /* and.b #imm,@(R0,GBR) */ in _decode_opc()
1140 tcg_gen_add_i32(addr, REG(0), cpu_gbr); in _decode_opc()
1147 case 0x8b00: /* bf label */ in _decode_opc()
1151 case 0x8f00: /* bf/s label */ in _decode_opc()
1157 case 0x8900: /* bt label */ in _decode_opc()
1161 case 0x8d00: /* bt/s label */ in _decode_opc()
1167 case 0x8800: /* cmp/eq #imm,R0 */ in _decode_opc()
1168 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); in _decode_opc()
1170 case 0xc400: /* mov.b @(disp,GBR),R0 */ in _decode_opc()
1174 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); in _decode_opc()
1177 case 0xc500: /* mov.w @(disp,GBR),R0 */ in _decode_opc()
1181 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW | MO_ALIGN); in _decode_opc()
1184 case 0xc600: /* mov.l @(disp,GBR),R0 */ in _decode_opc()
1188 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL | MO_ALIGN); in _decode_opc()
1191 case 0xc000: /* mov.b R0,@(disp,GBR) */ in _decode_opc()
1195 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); in _decode_opc()
1198 case 0xc100: /* mov.w R0,@(disp,GBR) */ in _decode_opc()
1202 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW | MO_ALIGN); in _decode_opc()
1205 case 0xc200: /* mov.l R0,@(disp,GBR) */ in _decode_opc()
1209 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL | MO_ALIGN); in _decode_opc()
1212 case 0x8000: /* mov.b R0,@(disp,Rn) */ in _decode_opc()
1216 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); in _decode_opc()
1219 case 0x8100: /* mov.w R0,@(disp,Rn) */ in _decode_opc()
1223 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, in _decode_opc()
1227 case 0x8400: /* mov.b @(disp,Rn),R0 */ in _decode_opc()
1231 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); in _decode_opc()
1234 case 0x8500: /* mov.w @(disp,Rn),R0 */ in _decode_opc()
1238 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, in _decode_opc()
1242 case 0xc700: /* mova @(disp,PC),R0 */ in _decode_opc()
1244 tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + in _decode_opc()
1247 case 0xcb00: /* or #imm,R0 */ in _decode_opc()
1248 tcg_gen_ori_i32(REG(0), REG(0), B7_0); in _decode_opc()
1250 case 0xcf00: /* or.b #imm,@(R0,GBR) */ in _decode_opc()
1254 tcg_gen_add_i32(addr, REG(0), cpu_gbr); in _decode_opc()
1261 case 0xc300: /* trapa #imm */ in _decode_opc()
1271 case 0xc800: /* tst #imm,R0 */ in _decode_opc()
1274 tcg_gen_andi_i32(val, REG(0), B7_0); in _decode_opc()
1275 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1278 case 0xcc00: /* tst.b #imm,@(R0,GBR) */ in _decode_opc()
1281 tcg_gen_add_i32(val, REG(0), cpu_gbr); in _decode_opc()
1284 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1287 case 0xca00: /* xor #imm,R0 */ in _decode_opc()
1288 tcg_gen_xori_i32(REG(0), REG(0), B7_0); in _decode_opc()
1290 case 0xce00: /* xor.b #imm,@(R0,GBR) */ in _decode_opc()
1294 tcg_gen_add_i32(addr, REG(0), cpu_gbr); in _decode_opc()
1303 switch (ctx->opcode & 0xf08f) { in _decode_opc()
1304 case 0x408e: /* ldc Rm,Rn_BANK */ in _decode_opc()
1308 case 0x4087: /* ldc.l @Rm+,Rn_BANK */ in _decode_opc()
1314 case 0x0082: /* stc Rm_BANK,Rn */ in _decode_opc()
1318 case 0x4083: /* stc.l Rm_BANK,@-Rn */ in _decode_opc()
1330 switch (ctx->opcode & 0xf0ff) { in _decode_opc()
1331 case 0x0023: /* braf Rn */ in _decode_opc()
1337 case 0x0003: /* bsrf Rn */ in _decode_opc()
1344 case 0x4015: /* cmp/pl Rn */ in _decode_opc()
1345 tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1347 case 0x4011: /* cmp/pz Rn */ in _decode_opc()
1348 tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1350 case 0x4010: /* dt Rn */ in _decode_opc()
1352 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1354 case 0x402b: /* jmp @Rn */ in _decode_opc()
1360 case 0x400b: /* jsr @Rn */ in _decode_opc()
1367 case 0x400e: /* ldc Rm,SR */ in _decode_opc()
1371 tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); in _decode_opc()
1376 case 0x4007: /* ldc.l @Rm+,SR */ in _decode_opc()
1382 tcg_gen_andi_i32(val, val, 0x700083f3); in _decode_opc()
1388 case 0x0002: /* stc SR,Rn */ in _decode_opc()
1392 case 0x4003: /* stc SR,@-Rn */ in _decode_opc()
1432 LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) in _decode_opc()
1433 LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) in _decode_opc()
1434 LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) in _decode_opc()
1435 LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) in _decode_opc()
1436 ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED) in _decode_opc()
1437 LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED CHECK_SH4A) in _decode_opc()
1438 LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) in _decode_opc()
1439 LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) in _decode_opc()
1440 LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) in _decode_opc()
1441 LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) in _decode_opc()
1442 LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) in _decode_opc()
1443 case 0x406a: /* lds Rm,FPSCR */ in _decode_opc()
1448 case 0x4066: /* lds.l @Rm+,FPSCR */ in _decode_opc()
1459 case 0x006a: /* sts FPSCR,Rn */ in _decode_opc()
1461 tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); in _decode_opc()
1463 case 0x4062: /* sts FPSCR,@-Rn */ in _decode_opc()
1468 tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); in _decode_opc()
1475 case 0x00c3: /* movca.l R0,@Rm */ in _decode_opc()
1481 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1486 case 0x40a9: /* movua.l @Rm,R0 */ in _decode_opc()
1489 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1492 case 0x40e9: /* movua.l @Rm+,R0 */ in _decode_opc()
1495 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1499 case 0x0029: /* movt Rn */ in _decode_opc()
1502 case 0x0073: in _decode_opc()
1506 * 0 -> LDST in _decode_opc()
1524 REG(0), ctx->memidx, in _decode_opc()
1529 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1536 tcg_gen_movi_i32(cpu_sr_t, 0); in _decode_opc()
1542 case 0x0063: in _decode_opc()
1547 * occurred 0 -> LDST in _decode_opc()
1555 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1557 tcg_gen_mov_i32(cpu_lock_value, REG(0)); in _decode_opc()
1560 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1562 tcg_gen_movi_i32(cpu_lock_addr, 0); in _decode_opc()
1565 case 0x0093: /* ocbi @Rn */ in _decode_opc()
1570 case 0x00a3: /* ocbp @Rn */ in _decode_opc()
1571 case 0x00b3: /* ocbwb @Rn */ in _decode_opc()
1576 case 0x0083: /* pref @Rn */ in _decode_opc()
1578 case 0x00d3: /* prefi @Rn */ in _decode_opc()
1581 case 0x00e3: /* icbi @Rn */ in _decode_opc()
1584 case 0x00ab: /* synco */ in _decode_opc()
1588 case 0x4024: /* rotcl Rn */ in _decode_opc()
1597 case 0x4025: /* rotcr Rn */ in _decode_opc()
1606 case 0x4004: /* rotl Rn */ in _decode_opc()
1608 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1610 case 0x4005: /* rotr Rn */ in _decode_opc()
1611 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1614 case 0x4000: /* shll Rn */ in _decode_opc()
1615 case 0x4020: /* shal Rn */ in _decode_opc()
1619 case 0x4021: /* shar Rn */ in _decode_opc()
1623 case 0x4001: /* shlr Rn */ in _decode_opc()
1627 case 0x4008: /* shll2 Rn */ in _decode_opc()
1630 case 0x4018: /* shll8 Rn */ in _decode_opc()
1633 case 0x4028: /* shll16 Rn */ in _decode_opc()
1636 case 0x4009: /* shlr2 Rn */ in _decode_opc()
1639 case 0x4019: /* shlr8 Rn */ in _decode_opc()
1642 case 0x4029: /* shlr16 Rn */ in _decode_opc()
1645 case 0x401b: /* tas.b @Rn */ in _decode_opc()
1647 tcg_constant_i32(0x80), ctx->memidx, MO_UB); in _decode_opc()
1648 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0); in _decode_opc()
1650 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ in _decode_opc()
1654 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ in _decode_opc()
1658 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ in _decode_opc()
1662 if (ctx->opcode & 0x0100) { in _decode_opc()
1673 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1677 if (ctx->opcode & 0x0100) { in _decode_opc()
1688 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ in _decode_opc()
1690 tcg_gen_xori_i32(FREG(B11_8), FREG(B11_8), 0x80000000); in _decode_opc()
1692 case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ in _decode_opc()
1694 tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff); in _decode_opc()
1696 case 0xf06d: /* fsqrt FRn */ in _decode_opc()
1699 if (ctx->opcode & 0x0100) { in _decode_opc()
1710 case 0xf07d: /* fsrra FRn */ in _decode_opc()
1715 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ in _decode_opc()
1718 tcg_gen_movi_i32(FREG(B11_8), 0); in _decode_opc()
1720 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ in _decode_opc()
1723 tcg_gen_movi_i32(FREG(B11_8), 0x3f800000); in _decode_opc()
1725 case 0xf0ad: /* fcnvsd FPUL,DRn */ in _decode_opc()
1733 case 0xf0bd: /* fcnvds DRn,FPUL */ in _decode_opc()
1741 case 0xf0ed: /* fipr FVm,FVn */ in _decode_opc()
1751 case 0xf0fd: /* ftrv XMTRX,FVn */ in _decode_opc()
1755 if ((ctx->opcode & 0x0300) != 0x0100) { in _decode_opc()
1764 #if 0 in _decode_opc()
1765 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", in _decode_opc()
1862 for (i = 0; i < max_insns; ++i) { in decode_gusa()
1872 i = 0; in decode_gusa()
1875 do { if (i >= max_insns) goto fail; ctx->opcode = insns[i++]; } while (0) in decode_gusa()
1881 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1882 case 0x6000: /* mov.b @Rm,Rn */ in decode_gusa()
1885 case 0x6001: /* mov.w @Rm,Rn */ in decode_gusa()
1888 case 0x6002: /* mov.l @Rm,Rn */ in decode_gusa()
1906 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1907 case 0x6003: /* mov Rm,Rn */ in decode_gusa()
1934 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1935 case 0x300c: /* add Rm,Rn */ in decode_gusa()
1938 case 0x2009: /* and Rm,Rn */ in decode_gusa()
1941 case 0x200a: /* xor Rm,Rn */ in decode_gusa()
1944 case 0x200b: /* or Rm,Rn */ in decode_gusa()
1952 if (op_src < 0) { in decode_gusa()
1967 case 0x6007: /* not Rm,Rn */ in decode_gusa()
1968 if (ld_dst != B7_4 || mv_src >= 0) { in decode_gusa()
1976 case 0x7000 ... 0x700f: /* add #imm,Rn */ in decode_gusa()
1977 if (op_dst != B11_8 || mv_src >= 0) { in decode_gusa()
1984 case 0x3000: /* cmp/eq Rm,Rn */ in decode_gusa()
1988 if ((ld_dst == B11_8) + (ld_dst == B7_4) != 1 || mv_src >= 0) { in decode_gusa()
1996 switch (ctx->opcode & 0xff00) { in decode_gusa()
1997 case 0x8b00: /* bf label */ in decode_gusa()
1998 case 0x8f00: /* bf/s label */ in decode_gusa()
2002 if ((ctx->opcode & 0xff00) == 0x8b00) { /* bf label */ in decode_gusa()
2009 if ((ctx->opcode & 0xf0ff) == 0x0029) { /* movt Rn */ in decode_gusa()
2021 case 0x2008: /* tst Rm,Rn */ in decode_gusa()
2023 if (ld_dst != B11_8 || ld_dst != B7_4 || mv_src >= 0) { in decode_gusa()
2027 op_arg = tcg_constant_i32(0); in decode_gusa()
2030 if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */ in decode_gusa()
2049 switch (ctx->opcode & 0xf00f) { in decode_gusa()
2050 case 0x2000: /* mov.b Rm,@Rn */ in decode_gusa()
2053 case 0x2001: /* mov.w Rm,@Rn */ in decode_gusa()
2056 case 0x2002: /* mov.l Rm,@Rn */ in decode_gusa()
2076 if (st_src == ld_dst || mv_src >= 0) { in decode_gusa()
2150 if (mt_dst >= 0) { in decode_gusa()
2198 ctx->memidx = (tbflags & (1u << SR_MD)) == 0 ? 1 : 0; in sh4_tr_init_disas_context()
2205 (tbflags & (1 << SR_RB))) * 0x10; in sh4_tr_init_disas_context()
2206 ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0; in sh4_tr_init_disas_context()
2292 tcg_gen_exit_tb(NULL, 0); in sh4_tr_tb_stop()
2297 gen_goto_tb(ctx, 0, ctx->base.pc_next); in sh4_tr_tb_stop()