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/linux-3.3/arch/mips/include/asm/mach-db1x00/
Dbcsr.h22 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
23 #define DB1000_BCSR_HEXLED_OFS 0x01000000
25 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
26 #define DB1550_BCSR_HEXLED_OFS 0x00400000
28 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
29 #define PB1550_BCSR_HEXLED_OFS 0x00800000
31 #define DB1200_BCSR_PHYS_ADDR 0x19800000
32 #define DB1200_BCSR_HEXLED_OFS 0x00400000
34 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
35 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux-3.3/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/linux-3.3/drivers/mtd/nand/
Dsm_common.c18 {.offset = 0 , .length = 4}, /* reserved */
32 .eccpos = {0, 1, 2},
44 int ret, error = 0; in sm_block_markbad()
47 oob.block_status = 0x0F; in sm_block_markbad()
52 ops.ooboffs = 0; in sm_block_markbad()
59 if (ret < 0 || ops.oobretlen != SM_OOB_SIZE) { in sm_block_markbad()
72 {"SmartMedia 1MiB 5V", 0x6e, 256, 1, 0x1000, 0},
73 {"SmartMedia 1MiB 3,3V", 0xe8, 256, 1, 0x1000, 0},
74 {"SmartMedia 1MiB 3,3V", 0xec, 256, 1, 0x1000, 0},
75 {"SmartMedia 2MiB 3,3V", 0xea, 256, 2, 0x1000, 0},
[all …]
Dnand_ids.c19 * Pagesize; 0, 256, 512
20 * 0 get this information from the extended chip ID
27 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
28 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
29 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
30 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
31 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
32 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
33 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
34 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
[all …]
/linux-3.3/arch/blackfin/include/asm/
Dbfin_can.h16 #define RECEIVE_STD_CHL 0
37 /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
49 __BFP(mc1); /* offset 0x00 */
50 __BFP(md1); /* offset 0x04 */
51 __BFP(trs1); /* offset 0x08 */
52 __BFP(trr1); /* offset 0x0c */
53 __BFP(ta1); /* offset 0x10 */
54 __BFP(aa1); /* offset 0x14 */
55 __BFP(rmp1); /* offset 0x18 */
56 __BFP(rml1); /* offset 0x1c */
[all …]
/linux-3.3/include/linux/mfd/wm8350/
Dcore.h31 #define WM8350_RESET_ID 0x00
32 #define WM8350_ID 0x01
33 #define WM8350_REVISION 0x02
34 #define WM8350_SYSTEM_CONTROL_1 0x03
35 #define WM8350_SYSTEM_CONTROL_2 0x04
36 #define WM8350_SYSTEM_HIBERNATE 0x05
37 #define WM8350_INTERFACE_CONTROL 0x06
38 #define WM8350_POWER_MGMT_1 0x08
39 #define WM8350_POWER_MGMT_2 0x09
40 #define WM8350_POWER_MGMT_3 0x0A
[all …]
Daudio.h18 #define WM8350_CLOCK_CONTROL_1 0x28
19 #define WM8350_CLOCK_CONTROL_2 0x29
20 #define WM8350_FLL_CONTROL_1 0x2A
21 #define WM8350_FLL_CONTROL_2 0x2B
22 #define WM8350_FLL_CONTROL_3 0x2C
23 #define WM8350_FLL_CONTROL_4 0x2D
24 #define WM8350_DAC_CONTROL 0x30
25 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
26 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
27 #define WM8350_DAC_LR_RATE 0x35
[all …]
/linux-3.3/drivers/gpu/drm/nouveau/
Dnv40_pm.c36 u32 ctrl = nv_rd32(dev, reg + 0x00); in read_pll_1()
37 int P = (ctrl & 0x00070000) >> 16; in read_pll_1()
38 int N = (ctrl & 0x0000ff00) >> 8; in read_pll_1()
39 int M = (ctrl & 0x000000ff) >> 0; in read_pll_1()
40 u32 ref = 27000, clk = 0; in read_pll_1()
42 if (ctrl & 0x80000000) in read_pll_1()
51 u32 ctrl = nv_rd32(dev, reg + 0x00); in read_pll_2()
52 u32 coef = nv_rd32(dev, reg + 0x04); in read_pll_2()
53 int N2 = (coef & 0xff000000) >> 24; in read_pll_2()
54 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2()
[all …]
Dnvc0_fifo.c57 for (i = 0, p = 0; i < 128; i++) { in nvc0_fifo_playlist_update()
58 if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1)) in nvc0_fifo_playlist_update()
60 nv_wo32(cur, p + 0, i); in nvc0_fifo_playlist_update()
61 nv_wo32(cur, p + 4, 0x00000004); in nvc0_fifo_playlist_update()
66 nv_wr32(dev, 0x002270, cur->vinst >> 12); in nvc0_fifo_playlist_update()
67 nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3)); in nvc0_fifo_playlist_update()
68 if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000)) in nvc0_fifo_playlist_update()
118 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, in nvc0_fifo_create_context()
123 nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000, in nvc0_fifo_create_context()
127 priv->user_vma.offset + (chan->id * 0x1000), in nvc0_fifo_create_context()
[all …]
/linux-3.3/arch/powerpc/boot/dts/
Dmpc8548cds.dts32 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
36 reg = <0 0xe0005000 0 0x1000>;
40 ranges = <0 0x0 0xe0000000 0x100000>;
45 reg = <0x50>;
50 reg = <0x56>;
55 reg = <0x57>;
62 reg = <0x50>;
72 phy0: ethernet-phy@0 {
73 interrupts = <5 1 0 0>;
74 reg = <0x0>;
[all …]
/linux-3.3/include/linux/mfd/
Dwm8400-private.h30 #define WM8400_REGISTER_COUNT 0x55
46 #define WM8400_RESET_ID 0x00
47 #define WM8400_ID 0x01
48 #define WM8400_POWER_MANAGEMENT_1 0x02
49 #define WM8400_POWER_MANAGEMENT_2 0x03
50 #define WM8400_POWER_MANAGEMENT_3 0x04
51 #define WM8400_AUDIO_INTERFACE_1 0x05
52 #define WM8400_AUDIO_INTERFACE_2 0x06
53 #define WM8400_CLOCKING_1 0x07
54 #define WM8400_CLOCKING_2 0x08
[all …]
/linux-3.3/arch/arm/mach-s3c64xx/
Dmach-crag6410-module.c40 { WM5100_MICDET_MICBIAS3, 0, 0 },
45 0,
46 0,
47 0,
48 0,
49 0x2, /* IRQ: CMOS output */
50 0x3, /* CLKOUT: CMOS output */
59 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
60 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
61 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
[all …]
/linux-3.3/drivers/net/ethernet/atheros/atlx/
Datlx.h36 #define SPEED_0 0xffff
43 #define MEDIA_TYPE_AUTO_SENSOR 0
46 #define REG_PM_CTRLSTAT 0x44
48 #define REG_PCIE_CAP_LIST 0x58
50 #define REG_VPD_CAP 0x6C
51 #define VPD_CAP_ID_MASK 0xFF
52 #define VPD_CAP_ID_SHIFT 0
53 #define VPD_CAP_NEXT_PTR_MASK 0xFF
55 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
57 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/linux-3.3/drivers/staging/comedi/drivers/
Dni_tio_internal.h33 case 0: in NITIO_Gi_Autoincrement_Reg()
49 return 0; in NITIO_Gi_Autoincrement_Reg()
55 case 0: in NITIO_Gi_Command_Reg()
71 return 0; in NITIO_Gi_Command_Reg()
78 case 0: in NITIO_Gi_Counting_Mode_Reg()
94 return 0; in NITIO_Gi_Counting_Mode_Reg()
101 case 0: in NITIO_Gi_Input_Select_Reg()
117 return 0; in NITIO_Gi_Input_Select_Reg()
124 case 0: in NITIO_Gxx_Joint_Reset_Reg()
136 return 0; in NITIO_Gxx_Joint_Reset_Reg()
[all …]
/linux-3.3/arch/arm/mach-u300/include/mach/
Du300-regs.h28 #define U300_NAND_CS0_PHYS_BASE 0x80000000
31 #define U300_NAND_IF_PHYS_BASE 0x9f800000
34 #define U300_AHB_PER_PHYS_BASE 0xa0000000
35 #define U300_AHB_PER_VIRT_BASE 0xff010000
38 #define U300_FAST_PER_PHYS_BASE 0xc0000000
39 #define U300_FAST_PER_VIRT_BASE 0xff020000
42 #define U300_SLOW_PER_PHYS_BASE 0xc0010000
43 #define U300_SLOW_PER_VIRT_BASE 0xff000000
46 #define U300_BOOTROM_PHYS_BASE 0xffff0000
47 #define U300_BOOTROM_VIRT_BASE 0xffff0000
[all …]
/linux-3.3/drivers/tty/
Dmoxa.h4 #define MOXA 0x400
16 #define Magic_code 0x404
21 #define C218_ConfBase 0x800
22 #define C218_status (C218_ConfBase + 0) /* BIOS running status */
24 #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
27 #define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
28 #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
29 #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
30 #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
31 #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
[all …]
/linux-3.3/include/linux/mfd/wm831x/
Dirq.h19 #define WM831X_IRQ_TEMP_THW 0
80 * R16400 (0x4010) - System Interrupts
82 #define WM831X_PS_INT 0x8000 /* PS_INT */
83 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
86 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
87 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
90 #define WM831X_GP_INT 0x2000 /* GP_INT */
91 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
94 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
95 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/linux-3.3/arch/arm/mach-ux500/include/mach/
Ddb5500-regs.h10 #define U5500_PER1_BASE 0xA0020000
11 #define U5500_PER2_BASE 0xA0010000
12 #define U5500_PER3_BASE 0x80140000
13 #define U5500_PER4_BASE 0x80150000
14 #define U5500_PER5_BASE 0x80100000
15 #define U5500_PER6_BASE 0x80120000
17 #define U5500_GIC_DIST_BASE 0xA0411000
18 #define U5500_GIC_CPU_BASE 0xA0410100
19 #define U5500_DMA_BASE 0x90030000
20 #define U5500_STM_BASE 0x90020000
[all …]
Ddb8500-regs.h11 #define U8500_ESRAM_BASE 0x40000000
12 #define U8500_ESRAM_BANK_SIZE 0x00020000
22 #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
29 #define U8500_PER3_BASE 0x80000000
30 #define U8500_STM_BASE 0x80100000
31 #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
32 #define U8500_PER2_BASE 0x80110000
33 #define U8500_PER1_BASE 0x80120000
34 #define U8500_B2R2_BASE 0x80130000
35 #define U8500_HSEM_BASE 0x80140000
[all …]
/linux-3.3/arch/m68k/kernel/
Dsun3-head.S9 PSL_HIGHIPL = 0x2700
10 NBSG = 0x20000
11 ICACHE_ONLY = 0x00000009
12 CACHES_OFF = 0x00000008 | actually a clear and disable --m
26 swapper_pg_dir: .skip 0x2000
27 pg0: .skip 0x2000
28 kernel_pmd_table: .skip 0x2000
44 moveq #0, %d0
49 lea (AC_SEGMAP+0),%a0
67 /* Following code executes at high addresses (0xE000xxx). */
[all …]
/linux-3.3/drivers/net/ethernet/natsemi/
Dibmlana.h15 #define IBM_LANA_ID 0xffe0
46 #define IBM_LANA_IORANGE 0xa0
50 #define SONIC_CMDREG 0x00
51 #define CMDREG_HTX 0x0001 /* halt transmission */
52 #define CMDREG_TXP 0x0002 /* start transmission */
53 #define CMDREG_RXDIS 0x0004 /* disable receiver */
54 #define CMDREG_RXEN 0x0008 /* enable receiver */
55 #define CMDREG_STP 0x0010 /* stop timer */
56 #define CMDREG_ST 0x0020 /* start timer */
57 #define CMDREG_RST 0x0080 /* software reset */
[all …]
/linux-3.3/include/linux/
Dac97_codec.h8 #define AC97_RESET 0x0000 //
9 #define AC97_MASTER_VOL_STEREO 0x0002 // Line Out
10 #define AC97_HEADPHONE_VOL 0x0004 //
11 #define AC97_MASTER_VOL_MONO 0x0006 // TAD Output
12 #define AC97_MASTER_TONE 0x0008 //
13 #define AC97_PCBEEP_VOL 0x000a // none
14 #define AC97_PHONE_VOL 0x000c // TAD Input (mono)
15 #define AC97_MIC_VOL 0x000e // MIC Input (mono)
16 #define AC97_LINEIN_VOL 0x0010 // Line Input (stereo)
17 #define AC97_CD_VOL 0x0012 // CD Input (stereo)
[all …]
/linux-3.3/drivers/net/ethernet/amd/
Dam79c961a.h12 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
18 #define NET_DEBUG 0
21 #define NET_UID 0
22 #define NET_RDP 0x10
23 #define NET_RAP 0x12
24 #define NET_RESET 0x14
25 #define NET_IDP 0x16
30 #define CSR0 0
31 #define CSR0_INIT 0x0001
32 #define CSR0_STRT 0x0002
[all …]
/linux-3.3/drivers/net/ethernet/i825xx/
Deexpress.h10 #define DATAPORT 0x0000
11 #define WRITE_PTR 0x0002
12 #define READ_PTR 0x0004
13 #define SIGNAL_CA 0x0006
14 #define SET_IRQ 0x0007
15 #define SM_PTR 0x0008
16 #define MEM_Dec 0x000a
17 #define MEM_Ctrl 0x000b
18 #define MEM_Page_Ctrl 0x000c
19 #define Config 0x000d
[all …]
/linux-3.3/arch/m68k/platform/68328/
Dhead-ram.S14 #define ROM_OFFSET 0x10C00000
15 #define STACK_GAURD 0x10
21 movew #0x2700, %sr /* Exceptions off! */
23 #if 0
25 moveb #0x00, 0xfffffb0b /* Watchdog off */
26 moveb #0x10, 0xfffff000 /* SCR */
28 movew #0x2400, 0xfffff200 /* PLLCR */
29 movew #0x0123, 0xfffff202 /* PLLFSR */
31 moveb #0x00, 0xfffff40b /* enable chip select */
32 moveb #0x00, 0xfffff423 /* enable /DWE */
[all …]

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