Lines Matching +full:0 +full:x2000
19 #define WM831X_IRQ_TEMP_THW 0
80 * R16400 (0x4010) - System Interrupts
82 #define WM831X_PS_INT 0x8000 /* PS_INT */
83 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
86 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
87 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
90 #define WM831X_GP_INT 0x2000 /* GP_INT */
91 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
94 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
95 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
98 #define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
99 #define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
102 #define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
103 #define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
106 #define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
107 #define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
110 #define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
111 #define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
114 #define WM831X_PPM_INT 0x0080 /* PPM_INT */
115 #define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
118 #define WM831X_CS_INT 0x0040 /* CS_INT */
119 #define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
122 #define WM831X_RTC_INT 0x0020 /* RTC_INT */
123 #define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
126 #define WM831X_OTP_INT 0x0010 /* OTP_INT */
127 #define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
130 #define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
131 #define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
134 #define WM831X_CHG_INT 0x0004 /* CHG_INT */
135 #define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
138 #define WM831X_HC_INT 0x0002 /* HC_INT */
139 #define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
142 #define WM831X_UV_INT 0x0001 /* UV_INT */
143 #define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
144 #define WM831X_UV_INT_SHIFT 0 /* UV_INT */
148 * R16401 (0x4011) - Interrupt Status 1
150 #define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
151 #define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
154 #define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
155 #define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
158 #define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
159 #define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
162 #define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
163 #define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
166 #define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
167 #define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
170 #define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
171 #define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
174 #define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
175 #define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
178 #define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
179 #define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
182 #define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
183 #define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
186 #define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
187 #define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
190 #define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
191 #define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
194 #define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
195 #define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
198 #define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
199 #define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
202 #define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
203 #define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
206 #define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
207 #define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
212 * R16402 (0x4012) - Interrupt Status 2
214 #define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
215 #define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
218 #define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
219 #define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
222 #define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
223 #define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
226 #define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
227 #define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
230 #define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
231 #define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
234 #define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
235 #define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
238 #define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
239 #define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
242 #define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
243 #define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
246 #define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
247 #define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
250 #define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
251 #define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
254 #define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
255 #define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
258 #define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
259 #define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
262 #define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
263 #define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
266 #define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
267 #define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
270 #define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
271 #define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
272 #define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
276 * R16403 (0x4013) - Interrupt Status 3
278 #define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
279 #define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
282 #define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
283 #define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
286 #define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
287 #define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
290 #define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
291 #define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
294 #define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
295 #define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
298 #define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
299 #define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
302 #define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
303 #define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
306 #define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
307 #define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
310 #define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
311 #define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
314 #define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
315 #define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
316 #define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
320 * R16404 (0x4014) - Interrupt Status 4
322 #define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
323 #define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
326 #define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
327 #define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
330 #define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
331 #define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
334 #define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
335 #define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
338 #define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
339 #define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
342 #define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
343 #define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
344 #define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
348 * R16405 (0x4015) - Interrupt Status 5
350 #define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
351 #define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
354 #define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
355 #define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
358 #define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
359 #define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
362 #define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
363 #define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
366 #define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
367 #define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
370 #define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
371 #define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
374 #define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
375 #define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
378 #define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
379 #define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
382 #define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
383 #define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
386 #define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
387 #define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
390 #define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
391 #define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
394 #define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
395 #define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
398 #define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
399 #define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
402 #define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
403 #define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
406 #define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
407 #define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
410 #define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
411 #define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
412 #define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
416 * R16407 (0x4017) - IRQ Config
418 #define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
419 #define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
422 #define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
423 #define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
424 #define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
428 * R16408 (0x4018) - System Interrupts Mask
430 #define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
431 #define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
434 #define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
435 #define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
438 #define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
439 #define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
442 #define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
443 #define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
446 #define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
447 #define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
450 #define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
451 #define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
454 #define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
455 #define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
458 #define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
459 #define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
462 #define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
463 #define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
466 #define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
467 #define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
470 #define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
471 #define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
474 #define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
475 #define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
478 #define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
479 #define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
482 #define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
483 #define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
486 #define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
487 #define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
490 #define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
491 #define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
492 #define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
496 * R16409 (0x4019) - Interrupt Status 1 Mask
498 #define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
499 #define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
502 #define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
503 #define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
506 #define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
507 #define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
510 #define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
511 #define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
514 #define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
515 #define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
518 #define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
519 #define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
522 #define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
523 #define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
526 #define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
527 #define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
530 #define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
531 #define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
534 #define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
535 #define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
538 #define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
539 #define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
542 #define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
543 #define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
546 #define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
547 #define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
550 #define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
551 #define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
554 #define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
555 #define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
560 * R16410 (0x401A) - Interrupt Status 2 Mask
562 #define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
563 #define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
566 #define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
567 #define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
570 #define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
571 #define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
574 #define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
575 #define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
578 #define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
579 #define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
582 #define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
583 #define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
586 #define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
587 #define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
590 #define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
591 #define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
594 #define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
595 #define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
598 #define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
599 #define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
602 #define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
603 #define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
606 #define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
607 #define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
610 #define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
611 #define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
614 #define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
615 #define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
618 #define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
619 #define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
620 #define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
624 * R16411 (0x401B) - Interrupt Status 3 Mask
626 #define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
627 #define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
630 #define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
631 #define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
634 #define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
635 #define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
638 #define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
639 #define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
642 #define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
643 #define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
646 #define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
647 #define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
650 #define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
651 #define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
654 #define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
655 #define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
658 #define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
659 #define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
662 #define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
663 #define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
664 #define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
668 * R16412 (0x401C) - Interrupt Status 4 Mask
670 #define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
671 #define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
674 #define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
675 #define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
678 #define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
679 #define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
682 #define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
683 #define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
686 #define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
687 #define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
690 #define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
691 #define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
692 #define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
696 * R16413 (0x401D) - Interrupt Status 5 Mask
698 #define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
699 #define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
702 #define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
703 #define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
706 #define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
707 #define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
710 #define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
711 #define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
714 #define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
715 #define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
718 #define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
719 #define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
722 #define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
723 #define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
726 #define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
727 #define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
730 #define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
731 #define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
734 #define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
735 #define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
738 #define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
739 #define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
742 #define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
743 #define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
746 #define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
747 #define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
750 #define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
751 #define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
754 #define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
755 #define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
758 #define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
759 #define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
760 #define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */