Lines Matching +full:0 +full:x2000
28 #define U300_NAND_CS0_PHYS_BASE 0x80000000
31 #define U300_NAND_IF_PHYS_BASE 0x9f800000
34 #define U300_AHB_PER_PHYS_BASE 0xa0000000
35 #define U300_AHB_PER_VIRT_BASE 0xff010000
38 #define U300_FAST_PER_PHYS_BASE 0xc0000000
39 #define U300_FAST_PER_VIRT_BASE 0xff020000
42 #define U300_SLOW_PER_PHYS_BASE 0xc0010000
43 #define U300_SLOW_PER_VIRT_BASE 0xff000000
46 #define U300_BOOTROM_PHYS_BASE 0xffff0000
47 #define U300_BOOTROM_VIRT_BASE 0xffff0000
51 #define U300_SEMI_CONFIG_BASE 0x2FFE0000
53 #define U300_SEMI_CONFIG_BASE 0x30000000
61 #define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
63 /* Vectored Interrupt Controller 0, servicing 32 interrupts */
64 #define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
65 #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
68 #define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
69 #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
72 #define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
75 #define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
83 #define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
86 #define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
89 #define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
92 #define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
95 #define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
98 #define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
101 #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
105 #define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
116 #define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
117 #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
120 #define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
123 #define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
126 #define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
127 #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
130 #define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
133 #define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
136 #define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
139 #define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
142 #define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
145 #define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
148 #define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
157 #define U300_ISP_BASE (0xA0008000)
161 #define U300_DMAC_BASE (0xC0020000)
164 #define U300_MSL_BASE (0xc0022000)
167 #define U300_APEX_BASE (0xc0030000)
171 #define U300_VIDEOENC_BASE (0xc0080000)
173 #define U300_VIDEOENC_BASE (0xc0040000)
177 #define U300_XGAM_BASE (0xd0000000)