Lines Matching +full:0 +full:x2000
30 #define WM8400_REGISTER_COUNT 0x55
46 #define WM8400_RESET_ID 0x00
47 #define WM8400_ID 0x01
48 #define WM8400_POWER_MANAGEMENT_1 0x02
49 #define WM8400_POWER_MANAGEMENT_2 0x03
50 #define WM8400_POWER_MANAGEMENT_3 0x04
51 #define WM8400_AUDIO_INTERFACE_1 0x05
52 #define WM8400_AUDIO_INTERFACE_2 0x06
53 #define WM8400_CLOCKING_1 0x07
54 #define WM8400_CLOCKING_2 0x08
55 #define WM8400_AUDIO_INTERFACE_3 0x09
56 #define WM8400_AUDIO_INTERFACE_4 0x0A
57 #define WM8400_DAC_CTRL 0x0B
58 #define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C
59 #define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D
60 #define WM8400_DIGITAL_SIDE_TONE 0x0E
61 #define WM8400_ADC_CTRL 0x0F
62 #define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10
63 #define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11
64 #define WM8400_GPIO_CTRL_1 0x12
65 #define WM8400_GPIO1_GPIO2 0x13
66 #define WM8400_GPIO3_GPIO4 0x14
67 #define WM8400_GPIO5_GPIO6 0x15
68 #define WM8400_GPIOCTRL_2 0x16
69 #define WM8400_GPIO_POL 0x17
70 #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18
71 #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19
72 #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
73 #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
74 #define WM8400_LEFT_OUTPUT_VOLUME 0x1C
75 #define WM8400_RIGHT_OUTPUT_VOLUME 0x1D
76 #define WM8400_LINE_OUTPUTS_VOLUME 0x1E
77 #define WM8400_OUT3_4_VOLUME 0x1F
78 #define WM8400_LEFT_OPGA_VOLUME 0x20
79 #define WM8400_RIGHT_OPGA_VOLUME 0x21
80 #define WM8400_SPEAKER_VOLUME 0x22
81 #define WM8400_CLASSD1 0x23
82 #define WM8400_CLASSD3 0x25
83 #define WM8400_INPUT_MIXER1 0x27
84 #define WM8400_INPUT_MIXER2 0x28
85 #define WM8400_INPUT_MIXER3 0x29
86 #define WM8400_INPUT_MIXER4 0x2A
87 #define WM8400_INPUT_MIXER5 0x2B
88 #define WM8400_INPUT_MIXER6 0x2C
89 #define WM8400_OUTPUT_MIXER1 0x2D
90 #define WM8400_OUTPUT_MIXER2 0x2E
91 #define WM8400_OUTPUT_MIXER3 0x2F
92 #define WM8400_OUTPUT_MIXER4 0x30
93 #define WM8400_OUTPUT_MIXER5 0x31
94 #define WM8400_OUTPUT_MIXER6 0x32
95 #define WM8400_OUT3_4_MIXER 0x33
96 #define WM8400_LINE_MIXER1 0x34
97 #define WM8400_LINE_MIXER2 0x35
98 #define WM8400_SPEAKER_MIXER 0x36
99 #define WM8400_ADDITIONAL_CONTROL 0x37
100 #define WM8400_ANTIPOP1 0x38
101 #define WM8400_ANTIPOP2 0x39
102 #define WM8400_MICBIAS 0x3A
103 #define WM8400_FLL_CONTROL_1 0x3C
104 #define WM8400_FLL_CONTROL_2 0x3D
105 #define WM8400_FLL_CONTROL_3 0x3E
106 #define WM8400_FLL_CONTROL_4 0x3F
107 #define WM8400_LDO1_CONTROL 0x41
108 #define WM8400_LDO2_CONTROL 0x42
109 #define WM8400_LDO3_CONTROL 0x43
110 #define WM8400_LDO4_CONTROL 0x44
111 #define WM8400_DCDC1_CONTROL_1 0x46
112 #define WM8400_DCDC1_CONTROL_2 0x47
113 #define WM8400_DCDC2_CONTROL_1 0x48
114 #define WM8400_DCDC2_CONTROL_2 0x49
115 #define WM8400_INTERFACE 0x4B
116 #define WM8400_PM_GENERAL 0x4C
117 #define WM8400_PM_SHUTDOWN_CONTROL 0x4E
118 #define WM8400_INTERRUPT_STATUS_1 0x4F
119 #define WM8400_INTERRUPT_STATUS_1_MASK 0x50
120 #define WM8400_INTERRUPT_LEVELS 0x51
121 #define WM8400_SHUTDOWN_REASON 0x52
122 #define WM8400_LINE_CIRCUITS 0x54
129 * R0 (0x00) - Reset/ID
131 #define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */
132 #define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */
133 #define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */
136 * R1 (0x01) - ID
138 #define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */
143 * R18 (0x12) - GPIO CTRL 1
145 #define WM8400_IRQ 0x1000 /* IRQ */
146 #define WM8400_IRQ_MASK 0x1000 /* IRQ */
149 #define WM8400_TEMPOK 0x0800 /* TEMPOK */
150 #define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */
153 #define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */
154 #define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */
157 #define WM8400_MIC1DET 0x0200 /* MIC1DET */
158 #define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */
161 #define WM8400_FLL_LCK 0x0100 /* FLL_LCK */
162 #define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */
165 #define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */
166 #define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */
167 #define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */
170 * R19 (0x13) - GPIO1 & GPIO2
172 #define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
173 #define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */
176 #define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
177 #define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */
180 #define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */
181 #define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */
184 #define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */
185 #define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */
188 #define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
191 #define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
192 #define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */
195 #define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
196 #define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */
199 #define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */
200 #define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
203 #define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */
204 #define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
207 #define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
208 #define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
209 #define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
212 * R20 (0x14) - GPIO3 & GPIO4
214 #define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
215 #define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */
218 #define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
219 #define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */
222 #define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */
223 #define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */
226 #define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */
227 #define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */
230 #define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
233 #define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
234 #define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */
237 #define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
238 #define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */
241 #define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */
242 #define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
245 #define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */
246 #define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
249 #define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
250 #define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
251 #define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
254 * R21 (0x15) - GPIO5 & GPIO6
256 #define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
257 #define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */
260 #define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
261 #define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */
264 #define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */
265 #define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */
268 #define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */
269 #define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */
272 #define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
275 #define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
276 #define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */
279 #define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
280 #define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */
283 #define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */
284 #define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */
287 #define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */
288 #define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */
291 #define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
292 #define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */
293 #define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */
296 * R22 (0x16) - GPIOCTRL 2
298 #define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
299 #define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */
302 #define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */
303 #define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */
306 #define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */
307 #define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */
310 #define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */
311 #define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */
314 #define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
315 #define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */
318 #define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
319 #define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */
322 #define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */
323 #define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */
326 #define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
327 #define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */
330 #define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
331 #define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */
334 #define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */
335 #define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */
336 #define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */
340 * R23 (0x17) - GPIO_POL
342 #define WM8400_IRQ_INV 0x1000 /* IRQ_INV */
343 #define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */
346 #define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */
347 #define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */
350 #define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */
351 #define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */
354 #define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */
355 #define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */
358 #define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */
359 #define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */
362 #define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */
363 #define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */
364 #define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */
367 * R65 (0x41) - LDO 1 Control
369 #define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */
370 #define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */
373 #define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */
374 #define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */
377 #define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */
378 #define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */
381 #define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */
382 #define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */
385 #define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */
386 #define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */
389 #define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */
392 #define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */
393 #define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */
394 #define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */
397 * R66 (0x42) - LDO 2 Control
399 #define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */
400 #define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */
403 #define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */
404 #define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */
407 #define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */
408 #define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */
411 #define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */
412 #define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */
415 #define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */
416 #define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */
419 #define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */
422 #define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */
423 #define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */
424 #define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */
427 * R67 (0x43) - LDO 3 Control
429 #define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */
430 #define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */
433 #define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */
434 #define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */
437 #define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */
438 #define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */
441 #define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */
442 #define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */
445 #define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */
446 #define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */
449 #define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */
452 #define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */
453 #define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */
454 #define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */
457 * R68 (0x44) - LDO 4 Control
459 #define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */
460 #define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */
463 #define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */
464 #define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */
467 #define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */
468 #define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */
471 #define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */
472 #define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */
475 #define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */
476 #define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */
479 #define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */
482 #define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */
483 #define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */
484 #define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */
487 * R70 (0x46) - DCDC1 Control 1
489 #define WM8400_DC1_ENA 0x8000 /* DC1_ENA */
490 #define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */
493 #define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */
494 #define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */
497 #define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */
498 #define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */
501 #define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */
502 #define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */
505 #define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */
506 #define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */
509 #define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */
510 #define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */
513 #define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */
516 #define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */
517 #define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */
520 #define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */
521 #define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */
522 #define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */
525 * R71 (0x47) - DCDC1 Control 2
527 #define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */
528 #define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */
531 #define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */
534 #define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */
535 #define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */
538 #define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */
539 #define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */
540 #define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */
543 * R72 (0x48) - DCDC2 Control 1
545 #define WM8400_DC2_ENA 0x8000 /* DC2_ENA */
546 #define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */
549 #define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */
550 #define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */
553 #define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */
554 #define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */
557 #define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */
558 #define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */
561 #define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */
562 #define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */
565 #define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */
566 #define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */
569 #define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */
572 #define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */
573 #define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */
576 #define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */
577 #define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */
578 #define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */
581 * R73 (0x49) - DCDC2 Control 2
583 #define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */
584 #define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */
587 #define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */
590 #define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */
591 #define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */
594 #define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */
595 #define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */
596 #define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */
599 * R75 (0x4B) - Interface
601 #define WM8400_AUTOINC 0x0008 /* AUTOINC */
602 #define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */
605 #define WM8400_ARA_ENA 0x0004 /* ARA_ENA */
606 #define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */
609 #define WM8400_SPI_CFG 0x0002 /* SPI_CFG */
610 #define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */
615 * R76 (0x4C) - PM GENERAL
617 #define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */
618 #define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */
621 #define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */
622 #define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */
625 #define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */
626 #define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */
629 #define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */
630 #define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */
633 #define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */
634 #define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */
637 #define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */
638 #define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */
639 #define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */
642 * R78 (0x4E) - PM Shutdown Control
644 #define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */
645 #define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */
648 #define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */
649 #define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */
652 #define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */
653 #define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */
656 #define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */
657 #define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */
662 * R79 (0x4F) - Interrupt Status 1
664 #define WM8400_MICD_CINT 0x8000 /* MICD_CINT */
665 #define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */
668 #define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */
669 #define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */
672 #define WM8400_JDL_CINT 0x2000 /* JDL_CINT */
673 #define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */
676 #define WM8400_JDR_CINT 0x1000 /* JDR_CINT */
677 #define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */
680 #define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */
681 #define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */
684 #define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */
685 #define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */
688 #define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */
689 #define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */
692 #define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */
693 #define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */
696 #define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */
697 #define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */
700 #define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */
701 #define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */
704 #define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */
705 #define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */
708 #define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */
709 #define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */
712 #define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */
713 #define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */
716 #define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */
717 #define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */
720 #define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */
721 #define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */
724 #define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */
725 #define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */
726 #define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */
730 * R80 (0x50) - Interrupt Status 1 Mask
732 #define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */
733 #define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */
736 #define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */
737 #define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */
740 #define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */
741 #define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */
744 #define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */
745 #define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */
748 #define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */
749 #define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */
752 #define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */
753 #define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */
756 #define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */
757 #define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */
760 #define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */
761 #define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */
764 #define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */
765 #define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */
768 #define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */
769 #define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */
772 #define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */
773 #define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */
776 #define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */
777 #define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */
780 #define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */
781 #define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */
784 #define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */
785 #define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */
788 #define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */
789 #define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */
792 #define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */
793 #define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */
794 #define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */
798 * R81 (0x51) - Interrupt Levels
800 #define WM8400_MICD_LVL 0x8000 /* MICD_LVL */
801 #define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */
804 #define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */
805 #define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */
808 #define WM8400_JDL_LVL 0x2000 /* JDL_LVL */
809 #define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */
812 #define WM8400_JDR_LVL 0x1000 /* JDR_LVL */
813 #define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */
816 #define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */
817 #define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */
820 #define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */
821 #define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */
824 #define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */
825 #define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */
828 #define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */
829 #define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */
832 #define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */
833 #define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */
836 #define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */
837 #define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */
840 #define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */
841 #define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */
844 #define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */
845 #define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */
848 #define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */
849 #define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */
852 #define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */
853 #define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */
856 #define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */
857 #define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */
860 #define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */
861 #define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */
862 #define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */
866 * R82 (0x52) - Shutdown Reason
868 #define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */
869 #define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */
872 #define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */
873 #define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */
876 #define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */
877 #define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */
880 #define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */
881 #define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */
884 #define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */
885 #define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */
888 #define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */
889 #define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */
892 #define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */
893 #define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */
896 #define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */
897 #define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */
900 #define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */
901 #define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */
904 #define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */
905 #define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */
908 #define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */
909 #define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */
912 #define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */
913 #define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */
914 #define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */
918 * R84 (0x54) - Line Circuits
920 #define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */
921 #define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */
924 #define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */
927 #define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */
928 #define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */
929 #define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */