36 	u32 ctrl = nv_rd32(dev, reg + 0x00);  in read_pll_1()
37 	int P = (ctrl & 0x00070000) >> 16;  in read_pll_1()
38 	int N = (ctrl & 0x0000ff00) >> 8;  in read_pll_1()
39 	int M = (ctrl & 0x000000ff) >> 0;  in read_pll_1()
40 	u32 ref = 27000, clk = 0;  in read_pll_1()
42 	if (ctrl & 0x80000000)  in read_pll_1()
51 	u32 ctrl = nv_rd32(dev, reg + 0x00);  in read_pll_2()
52 	u32 coef = nv_rd32(dev, reg + 0x04);  in read_pll_2()
53 	int N2 = (coef & 0xff000000) >> 24;  in read_pll_2()
54 	int M2 = (coef & 0x00ff0000) >> 16;  in read_pll_2()
55 	int N1 = (coef & 0x0000ff00) >> 8;  in read_pll_2()
56 	int M1 = (coef & 0x000000ff) >> 0;  in read_pll_2()
57 	int P = (ctrl & 0x00070000) >> 16;  in read_pll_2()
58 	u32 ref = 27000, clk = 0;  in read_pll_2()
60 	if ((ctrl & 0x80000000) && M1) {  in read_pll_2()
62 		if ((ctrl & 0x40000100) == 0x40000000) {  in read_pll_2()
66 				clk = 0;  in read_pll_2()
78 		return read_pll_2(dev, 0x004000);  in read_clk()
80 		return read_pll_1(dev, 0x004008);  in read_clk()
85 	return 0;  in read_clk()
91 	u32 ctrl = nv_rd32(dev, 0x00c040);  in nv40_pm_clocks_get()
93 	perflvl->core   = read_clk(dev, (ctrl & 0x00000003) >> 0);  in nv40_pm_clocks_get()
94 	perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4);  in nv40_pm_clocks_get()
95 	perflvl->memory = read_pll_2(dev, 0x4020);  in nv40_pm_clocks_get()
96 	return 0;  in nv40_pm_clocks_get()
120 		pll->vco2.maxfreq = 0;  in nv40_calc_pll()
123 	if (ret == 0)  in nv40_calc_pll()
138 	return 0;  in nv40_calc_pll()
154 	ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core,  in nv40_pm_clocks_pre()
156 	if (ret < 0)  in nv40_pm_clocks_pre()
160 		info->npll_ctrl = 0x80000100 | (log2P << 16);  in nv40_pm_clocks_pre()
163 		info->npll_ctrl = 0xc0000000 | (log2P << 16);  in nv40_pm_clocks_pre()
169 		ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader,  in nv40_pm_clocks_pre()
171 		if (ret < 0)  in nv40_pm_clocks_pre()
174 		info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;  in nv40_pm_clocks_pre()
175 		info->ctrl = 0x00000223;  in nv40_pm_clocks_pre()
177 		info->spll = 0x00000000;  in nv40_pm_clocks_pre()
178 		info->ctrl = 0x00000333;  in nv40_pm_clocks_pre()
183 		info->mpll_ctrl = 0x00000000;  in nv40_pm_clocks_pre()
187 	ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,  in nv40_pm_clocks_pre()
189 	if (ret < 0)  in nv40_pm_clocks_pre()
192 	info->mpll_ctrl  = 0x80000000 | (log2P << 16);  in nv40_pm_clocks_pre()
195 		info->mpll_ctrl |= 0x00000100;  in nv40_pm_clocks_pre()
198 		info->mpll_ctrl |= 0x40000000;  in nv40_pm_clocks_pre()
203 	if (ret < 0) {  in nv40_pm_clocks_pre()
215 	if ((nv_rd32(dev, 0x400760) & 0x000000f0) >> 4 !=  in nv40_pm_gr_idle()
216 	    (nv_rd32(dev, 0x400760) & 0x0000000f))  in nv40_pm_gr_idle()
219 	if (nv_rd32(dev, 0x400700))  in nv40_pm_gr_idle()
232 	u32 crtc_mask = 0;  in nv40_pm_clocks_set()
237 	for (i = 0; i < 2; i++) {  in nv40_pm_clocks_set()
238 		u32 vbl = nv_rd32(dev, 0x600808 + (i * 0x2000));  in nv40_pm_clocks_set()
239 		u32 cnt = 0;  in nv40_pm_clocks_set()
241 			if (vbl != nv_rd32(dev, 0x600808 + (i * 0x2000))) {  in nv40_pm_clocks_set()
242 				nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_pm_clocks_set()
243 				sr1[i] = nv_rd08(dev, 0x0c03c5 + (i * 0x2000));  in nv40_pm_clocks_set()
244 				if (!(sr1[i] & 0x20))  in nv40_pm_clocks_set()
254 	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);  in nv40_pm_clocks_set()
255 	if (!nv_wait(dev, 0x002500, 0x00000010, 0x00000000))  in nv40_pm_clocks_set()
257 	nv_mask(dev, 0x003220, 0x00000001, 0x00000000);  in nv40_pm_clocks_set()
258 	if (!nv_wait(dev, 0x003220, 0x00000010, 0x00000000))  in nv40_pm_clocks_set()
260 	nv_mask(dev, 0x003200, 0x00000001, 0x00000000);  in nv40_pm_clocks_set()
266 	ret = 0;  in nv40_pm_clocks_set()
269 	nv_mask(dev, 0x00c040, 0x00000333, 0x00000000);  in nv40_pm_clocks_set()
270 	nv_wr32(dev, 0x004004, info->npll_coef);  in nv40_pm_clocks_set()
271 	nv_mask(dev, 0x004000, 0xc0070100, info->npll_ctrl);  in nv40_pm_clocks_set()
272 	nv_mask(dev, 0x004008, 0xc007ffff, info->spll);  in nv40_pm_clocks_set()
274 	nv_mask(dev, 0x00c040, 0x00000333, info->ctrl);  in nv40_pm_clocks_set()
280 	for (i = 0; i < 2; i++) {  in nv40_pm_clocks_set()
283 		nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);  in nv40_pm_clocks_set()
284 		nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);  in nv40_pm_clocks_set()
285 		nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_pm_clocks_set()
286 		nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);  in nv40_pm_clocks_set()
290 	nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */  in nv40_pm_clocks_set()
291 	nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */  in nv40_pm_clocks_set()
292 	nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */  in nv40_pm_clocks_set()
293 	nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */  in nv40_pm_clocks_set()
294 	nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */  in nv40_pm_clocks_set()
297 	nv_mask(dev, 0x00c040, 0x0000c000, 0x00000000);  in nv40_pm_clocks_set()
299 	case 0x40:  in nv40_pm_clocks_set()
300 	case 0x45:  in nv40_pm_clocks_set()
301 	case 0x41:  in nv40_pm_clocks_set()
302 	case 0x42:  in nv40_pm_clocks_set()
303 	case 0x47:  in nv40_pm_clocks_set()
304 		nv_mask(dev, 0x004044, 0xc0771100, info->mpll_ctrl);  in nv40_pm_clocks_set()
305 		nv_mask(dev, 0x00402c, 0xc0771100, info->mpll_ctrl);  in nv40_pm_clocks_set()
306 		nv_wr32(dev, 0x004048, info->mpll_coef);  in nv40_pm_clocks_set()
307 		nv_wr32(dev, 0x004030, info->mpll_coef);  in nv40_pm_clocks_set()
308 	case 0x43:  in nv40_pm_clocks_set()
309 	case 0x49:  in nv40_pm_clocks_set()
310 	case 0x4b:  in nv40_pm_clocks_set()
311 		nv_mask(dev, 0x004038, 0xc0771100, info->mpll_ctrl);  in nv40_pm_clocks_set()
312 		nv_wr32(dev, 0x00403c, info->mpll_coef);  in nv40_pm_clocks_set()
314 		nv_mask(dev, 0x004020, 0xc0771100, info->mpll_ctrl);  in nv40_pm_clocks_set()
315 		nv_wr32(dev, 0x004024, info->mpll_coef);  in nv40_pm_clocks_set()
319 	nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);  in nv40_pm_clocks_set()
322 	nv_wr32(dev, 0x1002dc, 0x00000000);  in nv40_pm_clocks_set()
323 	nv_mask(dev, 0x100210, 0x80000000, 0x80000000);  in nv40_pm_clocks_set()
328 		nouveau_bios_init_exec(dev, ROM16(M.data[0]));  in nv40_pm_clocks_set()
333 	for (i = 0; i < 2; i++) {  in nv40_pm_clocks_set()
336 		nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);  in nv40_pm_clocks_set()
337 		nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_pm_clocks_set()
338 		nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i]);  in nv40_pm_clocks_set()
343 	nv_wr32(dev, 0x003250, 0x00000001);  in nv40_pm_clocks_set()
344 	nv_mask(dev, 0x003220, 0x00000001, 0x00000001);  in nv40_pm_clocks_set()
345 	nv_wr32(dev, 0x003200, 0x00000001);  in nv40_pm_clocks_set()
346 	nv_wr32(dev, 0x002500, 0x00000001);  in nv40_pm_clocks_set()
357 		u32 reg = nv_rd32(dev, 0x0010f0);  in nv40_pm_pwm_get()
358 		if (reg & 0x80000000) {  in nv40_pm_pwm_get()
359 			*duty = (reg & 0x7fff0000) >> 16;  in nv40_pm_pwm_get()
360 			*divs = (reg & 0x00007fff);  in nv40_pm_pwm_get()
361 			return 0;  in nv40_pm_pwm_get()
365 		u32 reg = nv_rd32(dev, 0x0015f4);  in nv40_pm_pwm_get()
366 		if (reg & 0x80000000) {  in nv40_pm_pwm_get()
367 			*divs = nv_rd32(dev, 0x0015f8);  in nv40_pm_pwm_get()
368 			*duty = (reg & 0x7fffffff);  in nv40_pm_pwm_get()
369 			return 0;  in nv40_pm_pwm_get()
383 		nv_wr32(dev, 0x0010f0, 0x80000000 | (duty << 16) | divs);  in nv40_pm_pwm_set()
386 		nv_wr32(dev, 0x0015f8, divs);  in nv40_pm_pwm_set()
387 		nv_wr32(dev, 0x0015f4, duty | 0x80000000);  in nv40_pm_pwm_set()
393 	return 0;  in nv40_pm_pwm_set()