57 	for (i = 0, p = 0; i < 128; i++) {  in nvc0_fifo_playlist_update()
58 		if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1))  in nvc0_fifo_playlist_update()
60 		nv_wo32(cur, p + 0, i);  in nvc0_fifo_playlist_update()
61 		nv_wo32(cur, p + 4, 0x00000004);  in nvc0_fifo_playlist_update()
66 	nv_wr32(dev, 0x002270, cur->vinst >> 12);  in nvc0_fifo_playlist_update()
67 	nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3));  in nvc0_fifo_playlist_update()
68 	if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000))  in nvc0_fifo_playlist_update()
118 	ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000,  in nvc0_fifo_create_context()
123 	nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000,  in nvc0_fifo_create_context()
127 				priv->user_vma.offset + (chan->id * 0x1000),  in nvc0_fifo_create_context()
136 				      chan->ramin->vinst, 0x100,  in nvc0_fifo_create_context()
141 	nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(fifoch->user->vinst));  in nvc0_fifo_create_context()
142 	nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(fifoch->user->vinst));  in nvc0_fifo_create_context()
143 	nv_wo32(fifoch->ramfc, 0x10, 0x0000face);  in nvc0_fifo_create_context()
144 	nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);  in nvc0_fifo_create_context()
145 	nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));  in nvc0_fifo_create_context()
146 	nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |  in nvc0_fifo_create_context()
148 	nv_wo32(fifoch->ramfc, 0x54, 0x00000002);  in nvc0_fifo_create_context()
149 	nv_wo32(fifoch->ramfc, 0x84, 0x20400000);  in nvc0_fifo_create_context()
150 	nv_wo32(fifoch->ramfc, 0x94, 0x30000001);  in nvc0_fifo_create_context()
151 	nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);  in nvc0_fifo_create_context()
152 	nv_wo32(fifoch->ramfc, 0xa4, 0x1f1f1f1f);  in nvc0_fifo_create_context()
153 	nv_wo32(fifoch->ramfc, 0xa8, 0x1f1f1f1f);  in nvc0_fifo_create_context()
154 	nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);  in nvc0_fifo_create_context()
155 	nv_wo32(fifoch->ramfc, 0xb8, 0xf8000000);  in nvc0_fifo_create_context()
156 	nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */  in nvc0_fifo_create_context()
157 	nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */  in nvc0_fifo_create_context()
160 	nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 |  in nvc0_fifo_create_context()
162 	nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001);  in nvc0_fifo_create_context()
164 	return 0;  in nvc0_fifo_create_context()
177 	nv_mask(dev, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000);  in nvc0_fifo_destroy_context()
178 	nv_wr32(dev, 0x002634, chan->id);  in nvc0_fifo_destroy_context()
179 	if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))  in nvc0_fifo_destroy_context()
180 		NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));  in nvc0_fifo_destroy_context()
184 	nv_wr32(dev, 0x003000 + (chan->id * 8), 0x00000000);  in nvc0_fifo_destroy_context()
204 	return 0;  in nvc0_fifo_load_context()
212 	for (i = 0; i < 128; i++) {  in nvc0_fifo_unload_context()
213 		if (!(nv_rd32(dev, 0x003004 + (i * 8)) & 1))  in nvc0_fifo_unload_context()
216 		nv_mask(dev, 0x003004 + (i * 8), 0x00000001, 0x00000000);  in nvc0_fifo_unload_context()
217 		nv_wr32(dev, 0x002634, i);  in nvc0_fifo_unload_context()
218 		if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {  in nvc0_fifo_unload_context()
219 			NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",  in nvc0_fifo_unload_context()
220 				i, nv_rd32(dev, 0x002634));  in nvc0_fifo_unload_context()
225 	return 0;  in nvc0_fifo_unload_context()
241 	nouveau_gpuobj_ref(NULL, &priv->playlist[0]);  in nvc0_fifo_destroy()
248 	nv_wr32(dev, 0x002140, 0x00000000);  in nvc0_fifo_takedown()
265 	ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,  in nvc0_fifo_create()
266 				 &priv->playlist[0]);  in nvc0_fifo_create()
270 	ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,  in nvc0_fifo_create()
275 	ret = nouveau_vm_get(dev_priv->bar1_vm, pfifo->channels * 0x1000,  in nvc0_fifo_create()
281 	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */  in nvc0_fifo_create()
282 	return 0;  in nvc0_fifo_create()
306 	nv_mask(dev, 0x000200, 0x00000100, 0x00000000);  in nvc0_fifo_init()
307 	nv_mask(dev, 0x000200, 0x00000100, 0x00000100);  in nvc0_fifo_init()
308 	nv_wr32(dev, 0x000204, 0xffffffff);  in nvc0_fifo_init()
309 	nv_wr32(dev, 0x002204, 0xffffffff);  in nvc0_fifo_init()
311 	priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204));  in nvc0_fifo_init()
316 		nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */  in nvc0_fifo_init()
317 		nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */  in nvc0_fifo_init()
318 		nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */  in nvc0_fifo_init()
319 		nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */  in nvc0_fifo_init()
320 		nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */  in nvc0_fifo_init()
321 		nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */  in nvc0_fifo_init()
325 	for (i = 0; i < priv->spoon_nr; i++) {  in nvc0_fifo_init()
326 		nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);  in nvc0_fifo_init()
327 		nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */  in nvc0_fifo_init()
328 		nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */  in nvc0_fifo_init()
331 	nv_mask(dev, 0x002200, 0x00000001, 0x00000001);  in nvc0_fifo_init()
332 	nv_wr32(dev, 0x002254, 0x10000000 | priv->user_vma.offset >> 12);  in nvc0_fifo_init()
334 	nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */  in nvc0_fifo_init()
335 	nv_wr32(dev, 0x002100, 0xffffffff);  in nvc0_fifo_init()
336 	nv_wr32(dev, 0x002140, 0xbfffffff);  in nvc0_fifo_init()
339 	for (i = 0; i < 128; i++) {  in nvc0_fifo_init()
344 		nv_wr32(dev, 0x003000 + (i * 8), 0xc0000000 |  in nvc0_fifo_init()
346 		nv_wr32(dev, 0x003004 + (i * 8), 0x001f0001);  in nvc0_fifo_init()
350 	return 0;  in nvc0_fifo_init()
354 	{ 0x00, "PGRAPH" },
355 	{ 0x03, "PEEPHOLE" },
356 	{ 0x04, "BAR1" },
357 	{ 0x05, "BAR3" },
358 	{ 0x07, "PFIFO" },
359 	{ 0x10, "PBSP" },
360 	{ 0x11, "PPPP" },
361 	{ 0x13, "PCOUNTER" },
362 	{ 0x14, "PVP" },
363 	{ 0x15, "PCOPY0" },
364 	{ 0x16, "PCOPY1" },
365 	{ 0x17, "PDAEMON" },
370 	{ 0x00, "PT_NOT_PRESENT" },
371 	{ 0x01, "PT_TOO_SHORT" },
372 	{ 0x02, "PAGE_NOT_PRESENT" },
373 	{ 0x03, "VM_LIMIT_EXCEEDED" },
374 	{ 0x04, "NO_CHANNEL" },
375 	{ 0x05, "PAGE_SYSTEM_ONLY" },
376 	{ 0x06, "PAGE_READ_ONLY" },
377 	{ 0x0a, "COMPRESSED_SYSRAM" },
378 	{ 0x0c, "INVALID_STORAGE_TYPE" },
383 	{ 0x01, "PCOPY0" },
384 	{ 0x02, "PCOPY1" },
385 	{ 0x04, "DISPATCH" },
386 	{ 0x05, "CTXCTL" },
387 	{ 0x06, "PFIFO" },
388 	{ 0x07, "BAR_READ" },
389 	{ 0x08, "BAR_WRITE" },
390 	{ 0x0b, "PVP" },
391 	{ 0x0c, "PPPP" },
392 	{ 0x0d, "PBSP" },
393 	{ 0x11, "PCOUNTER" },
394 	{ 0x12, "PDAEMON" },
395 	{ 0x14, "CCACHE" },
396 	{ 0x15, "CCACHE_POST" },
401 	{ 0x01, "TEX" },
402 	{ 0x0c, "ESETUP" },
403 	{ 0x0e, "CTXCTL" },
404 	{ 0x0f, "PROP" },
409 /*	{ 0x00008000, "" }	seen with null ib push */
410 	{ 0x00200000, "ILLEGAL_MTHD" },
411 	{ 0x00800000, "EMPTY_SUBC" },
418 	u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));  in nvc0_fifo_isr_vm_fault()
419 	u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));  in nvc0_fifo_isr_vm_fault()
420 	u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));  in nvc0_fifo_isr_vm_fault()
421 	u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));  in nvc0_fifo_isr_vm_fault()
422 	u32 client = (stat & 0x00001f00) >> 8;  in nvc0_fifo_isr_vm_fault()
424 	NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",  in nvc0_fifo_isr_vm_fault()
425 		(stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);  in nvc0_fifo_isr_vm_fault()
426 	nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);  in nvc0_fifo_isr_vm_fault()
429 	if (stat & 0x00000040) {  in nvc0_fifo_isr_vm_fault()
433 		printk("/GPC%d/", (stat & 0x1f000000) >> 24);  in nvc0_fifo_isr_vm_fault()
436 	printk(" on channel 0x%010llx\n", (u64)inst << 12);  in nvc0_fifo_isr_vm_fault()
442 	u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));  in nvc0_fifo_isr_subfifo_intr()
443 	u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));  in nvc0_fifo_isr_subfifo_intr()
444 	u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));  in nvc0_fifo_isr_subfifo_intr()
445 	u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;  in nvc0_fifo_isr_subfifo_intr()
446 	u32 subc = (addr & 0x00070000);  in nvc0_fifo_isr_subfifo_intr()
447 	u32 mthd = (addr & 0x00003ffc);  in nvc0_fifo_isr_subfifo_intr()
451 	NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",  in nvc0_fifo_isr_subfifo_intr()
454 	nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);  in nvc0_fifo_isr_subfifo_intr()
455 	nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);  in nvc0_fifo_isr_subfifo_intr()
461 	u32 stat = nv_rd32(dev, 0x002100);  in nvc0_fifo_isr()
463 	if (stat & 0x00000100) {  in nvc0_fifo_isr()
464 		NV_INFO(dev, "PFIFO: unknown status 0x00000100\n");  in nvc0_fifo_isr()
465 		nv_wr32(dev, 0x002100, 0x00000100);  in nvc0_fifo_isr()
466 		stat &= ~0x00000100;  in nvc0_fifo_isr()
469 	if (stat & 0x10000000) {  in nvc0_fifo_isr()
470 		u32 units = nv_rd32(dev, 0x00259c);  in nvc0_fifo_isr()
479 		nv_wr32(dev, 0x00259c, units);  in nvc0_fifo_isr()
480 		stat &= ~0x10000000;  in nvc0_fifo_isr()
483 	if (stat & 0x20000000) {  in nvc0_fifo_isr()
484 		u32 units = nv_rd32(dev, 0x0025a0);  in nvc0_fifo_isr()
493 		nv_wr32(dev, 0x0025a0, units);  in nvc0_fifo_isr()
494 		stat &= ~0x20000000;  in nvc0_fifo_isr()
497 	if (stat & 0x40000000) {  in nvc0_fifo_isr()
498 		NV_INFO(dev, "PFIFO: unknown status 0x40000000\n");  in nvc0_fifo_isr()
499 		nv_mask(dev, 0x002a00, 0x00000000, 0x00000000);  in nvc0_fifo_isr()
500 		stat &= ~0x40000000;  in nvc0_fifo_isr()
504 		NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);  in nvc0_fifo_isr()
505 		nv_wr32(dev, 0x002100, stat);  in nvc0_fifo_isr()
506 		nv_wr32(dev, 0x002140, 0);  in nvc0_fifo_isr()