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/linux-3.3/arch/arm/boot/dts/
Dversatile-ab.dts19 reg = <0x0 0x08000000>;
24 reg = <0x34000000 0x4000000>;
30 #size-cells = <0>;
32 reg = <0x10002000 0x1000>;
36 reg = <0x68>;
42 reg = <0x10010000 0x10000>;
48 reg = <0x10008000 0x1000>;
61 reg = <0x10140000 0x1000>;
68 reg = <0x10003000 0x1000>;
75 reg = <0x10130000 0x1000>;
[all …]
Dhighbank.dts20 /memreserve/ 0x00000000 0x0001000;
30 #size-cells = <0>;
32 cpu@0 {
34 reg = <0>;
60 reg = <0x00000000 0xff900000>;
76 reg = <0xfff10600 0x20>;
77 interrupts = <1 13 0xf04>;
82 reg = <0xfff10620 0x20>;
83 interrupts = <1 14 0xf04>;
89 #size-cells = <0>;
[all …]
Dversatile-pb.dts10 reg = <0x101e6000 0x1000>;
20 reg = <0x101e7000 0x1000>;
31 reg = <0x9000 0x1000>;
37 reg = <0xa000 0x1000>;
43 reg = <0xb000 0x1000>;
/linux-3.3/drivers/rapidio/devices/
Dtsi721.h26 #define DEFAULT_HOPCOUNT 0xff
27 #define DEFAULT_DESTID 0xff
30 #define PCI_DEVICE_ID_TSI721 0x80ab
32 #define BAR_0 0
40 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
41 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
48 #define RIO_TT_CODE_8 0x00000000
49 #define RIO_TT_CODE_16 0x00000001
59 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
69 #define TSI721_PCIECFG_MSIXTBL 0x0a4
[all …]
/linux-3.3/arch/mips/include/asm/mach-pnx8550/
Duart.h8 #define UART_BASE 0xbbe4a000 /* PNX8550 */
11 #define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
18 #define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
19 #define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
20 #define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
21 #define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
22 #define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
23 #define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
24 #define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
25 #define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
[all …]
/linux-3.3/arch/powerpc/boot/dts/fsl/
Dp3060si-post.dtsi37 interrupts = <25 2 0 0>;
42 /* controller at 0x200000 */
48 bus-range = <0x0 0xff>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
[all …]
Dp4080si-post.dtsi37 interrupts = <25 2 0 0>;
42 /* controller at 0x200000 */
48 bus-range = <0x0 0xff>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
[all …]
Dp5020si-post.dtsi37 interrupts = <25 2 0 0>;
42 /* controller at 0x200000 */
48 bus-range = <0x0 0xff>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
[all …]
Dp3041si-post.dtsi37 interrupts = <25 2 0 0>;
42 /* controller at 0x200000 */
48 bus-range = <0x0 0xff>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
[all …]
Dp2041si-post.dtsi37 interrupts = <25 2 0 0>;
42 /* controller at 0x200000 */
48 bus-range = <0x0 0xff>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
[all …]
Dp1023si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0xa000 */
48 bus-range = <0x0 0xff>;
50 interrupts = <16 2 0 0>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
57 interrupts = <16 2 0 0>;
61 /* controller at 0x9000 */
67 bus-range = <0 0xff>;
69 interrupts = <16 2 0 0>;
[all …]
Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/linux-3.3/include/linux/mfd/wm8350/
Dcomparator.h19 #define WM8350_DIGITISER_CONTROL_1 0x90
20 #define WM8350_DIGITISER_CONTROL_2 0x91
21 #define WM8350_AUX1_READBACK 0x98
22 #define WM8350_AUX2_READBACK 0x99
23 #define WM8350_AUX3_READBACK 0x9A
24 #define WM8350_AUX4_READBACK 0x9B
25 #define WM8350_CHIP_TEMP_READBACK 0x9F
26 #define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3
27 #define WM8350_GENERIC_COMPARATOR_1 0xA4
28 #define WM8350_GENERIC_COMPARATOR_2 0xA5
[all …]
/linux-3.3/arch/powerpc/include/asm/
Dtsi108.h22 #define TSI108_REG_SIZE (0x10000)
25 #define TSI108_HLP_SIZE 0x1000
26 #define TSI108_PCI_SIZE 0x1000
27 #define TSI108_CLK_SIZE 0x1000
28 #define TSI108_PB_SIZE 0x1000
29 #define TSI108_SD_SIZE 0x1000
30 #define TSI108_DMA_SIZE 0x1000
31 #define TSI108_ETH_SIZE 0x1000
32 #define TSI108_I2C_SIZE 0x400
33 #define TSI108_MPIC_SIZE 0x400
[all …]
/linux-3.3/arch/powerpc/boot/dts/
Dmpc8540ads.dts31 #size-cells = <0>;
33 PowerPC,8540@0 {
35 reg = <0x0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
49 reg = <0x0 0x8000000>; // 128M at 0x0
57 ranges = <0x0 0xe0000000 0x100000>;
[all …]
Dtqm8540.dts31 #size-cells = <0>;
33 PowerPC,8540@0 {
35 reg = <0>;
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
49 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
57 bus-frequency = <0>;
60 ecm-law@0 {
[all …]
Dsbc8560.dts34 #size-cells = <0>;
36 PowerPC,8560@0 {
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>;
45 clock-frequency = <0>;
[all …]
Dsbc8641d.dts37 #size-cells = <0>;
39 PowerPC,8641@0 {
41 reg = <0>;
46 timebase-frequency = <0>; // From uboot
47 bus-frequency = <0>; // From uboot
48 clock-frequency = <0>; // From uboot
57 timebase-frequency = <0>; // From uboot
58 bus-frequency = <0>; // From uboot
59 clock-frequency = <0>; // From uboot
65 reg = <0x00000000 0x20000000>; // 512M at 0x0
[all …]
Dxpedite5200.dts33 #size-cells = <0>;
35 PowerPC,8548@0 {
37 reg = <0>;
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
48 reg = <0x0 0x0>; // Filled in by U-Boot
55 ranges = <0x0 0xef000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
61 reg = <0x0 0x1000>;
[all …]
Dxpedite5200_xmon.dts21 boot-bank = <0x0>;
37 #size-cells = <0>;
39 PowerPC,8548@0 {
41 reg = <0>;
44 d-cache-size = <0x8000>; // L1, 32K
45 i-cache-size = <0x8000>; // L1, 32K
52 reg = <0x0 0x0>; // Filled in by boot loader
59 ranges = <0x0 0xef000000 0x100000>;
60 bus-frequency = <0>;
63 ecm-law@0 {
[all …]
Dtqm8548-bigflash.dts35 #size-cells = <0>;
37 PowerPC,8548@0 {
39 reg = <0>;
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xa0000000 0x100000>;
58 bus-frequency = <0>;
61 ecm-law@0 {
63 reg = <0x0 0x1000>;
[all …]
Dtqm8548.dts35 #size-cells = <0>;
37 PowerPC,8548@0 {
39 reg = <0>;
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xe0000000 0x100000>;
58 bus-frequency = <0>;
61 ecm-law@0 {
63 reg = <0x0 0x1000>;
[all …]
/linux-3.3/arch/arm/mach-ux500/include/mach/
Ddb5500-regs.h10 #define U5500_PER1_BASE 0xA0020000
11 #define U5500_PER2_BASE 0xA0010000
12 #define U5500_PER3_BASE 0x80140000
13 #define U5500_PER4_BASE 0x80150000
14 #define U5500_PER5_BASE 0x80100000
15 #define U5500_PER6_BASE 0x80120000
17 #define U5500_GIC_DIST_BASE 0xA0411000
18 #define U5500_GIC_CPU_BASE 0xA0410100
19 #define U5500_DMA_BASE 0x90030000
20 #define U5500_STM_BASE 0x90020000
[all …]
/linux-3.3/arch/mips/include/asm/mach-lantiq/xway/
Dlantiq_soc.h17 #define SOC_ID_DANUBE1 0x129
18 #define SOC_ID_DANUBE2 0x12B
19 #define SOC_ID_TWINPASS 0x12D
20 #define SOC_ID_AMAZON_SE 0x152
21 #define SOC_ID_ARX188 0x16C
22 #define SOC_ID_ARX168 0x16D
23 #define SOC_ID_ARX182 0x16F
26 #define SOC_TYPE_DANUBE 0x01
27 #define SOC_TYPE_TWINPASS 0x02
28 #define SOC_TYPE_AR9 0x03
[all …]
/linux-3.3/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]

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