boot/dts/xpedite5200_xmon.dts

21 	boot-bank = <0x0>;
37 		#size-cells = <0>;
39 		PowerPC,8548@0 {
41 			reg = <0>;
44 			d-cache-size = <0x8000>;	// L1, 32K
45 			i-cache-size = <0x8000>;	// L1, 32K
52 		reg = <0x0 0x0>;	// Filled in by boot loader
59 		ranges = <0x0 0xef000000 0x100000>;
60 		bus-frequency = <0>;
63 		ecm-law@0 {
65 			reg = <0x0 0x1000>;
71 			reg = <0x1000 0x1000>;
78 			reg = <0x2000 0x1000>;
85 			reg = <0x20000 0x1000>;
87 			cache-size = <0x80000>;	// L2, 512K
95 			#size-cells = <0>;
96 			cell-index = <0>;
98 			reg = <0x3000 0x100>;
105 			 * 	0: BRD_CFG0 (1: P14 IO present)
116 				reg = <0x18>;
119 				polarity = <0x00>;
125 				reg = <0x19>;
128 				polarity = <0x00>;
133 				reg = <0x50>;
139 				reg = <0x68>;
144 				reg = <0x34>;
151 			#size-cells = <0>;
154 			reg = <0x3100 0x100>;
164 			reg = <0x21300 0x4>;
165 			ranges = <0x0 0x21100 0x200>;
166 			cell-index = <0>;
167 			dma-channel@0 {
170 				reg = <0x0 0x80>;
171 				cell-index = <0>;
178 				reg = <0x80 0x80>;
186 				reg = <0x100 0x80>;
194 				reg = <0x180 0x80>;
201 		/* eTSEC1: Front panel port 0 */
205 			cell-index = <0>;
209 			reg = <0x24000 0x1000>;
210 			ranges = <0x0 0x24000 0x1000>;
219 				#size-cells = <0>;
221 				reg = <0x520 0x20>;
226 					reg = <0x1>;
231 					reg = <0x2>;
236 					reg = <0x3>;
241 					reg = <0x4>;
244 					reg = <0x11>;
258 			reg = <0x25000 0x1000>;
259 			ranges = <0x0 0x25000 0x1000>;
268 				#size-cells = <0>;
270 				reg = <0x520 0x20>;
273 					reg = <0x11>;
287 			reg = <0x26000 0x1000>;
288 			ranges = <0x0 0x26000 0x1000>;
297 				#size-cells = <0>;
299 				reg = <0x520 0x20>;
302 					reg = <0x11>;
316 			reg = <0x27000 0x1000>;
317 			ranges = <0x0 0x27000 0x1000>;
326 				#size-cells = <0>;
328 				reg = <0x520 0x20>;
331 					reg = <0x11>;
338 			cell-index = <0>;
341 			reg = <0x4500 0x100>;
342 			clock-frequency = <0>;
352 			reg = <0x4600 0x100>;
353 			clock-frequency = <0>;
361 			reg = <0xe0000 0x1000>;
367 			#address-cells = <0>;
369 			reg = <0x40000 0x40000>;
380 		reg = <0xef005000 0x100>;	// BRx, ORx, etc.
385 			0 0x0 0xf8000000 0x08000000	// NOR boot flash
386 			1 0x0 0xf0000000 0x08000000	// NOR expansion flash
387 			2 0x0 0xe8000000 0x00010000	// NAND CE1
388 			3 0x0 0xe8010000 0x00010000	// NAND CE2
391 		nor-boot@0,0 {
395 			reg = <0 0x0 0x4000000>;
398 			partition@0 {
400 				reg = <0x00000000 0x180000>;
404 				reg = <0x00180000 0x180000>;
408 				reg = <0x00300000 0x3c80000>;
412 				reg = <0x03f80000 0x80000>;
416 		nor-alternate@1,0 {
420 			reg = <1 0x0 0x4000000>;
423 			partition@0 {
425 				reg = <0x00000000 0x3f80000>;
429 				reg = <0x03f80000 0x80000>;
433 		nand@2,0 {
437 			reg = <2 0x0 0x10000>;
438 			cle-line = <0x8>;	/* CLE tied to A3 */
439 			ale-line = <0x10>;	/* ALE tied to A4 */
441 			partition@0 {
443 				reg = <0 0x40000000>;
455 		reg = <0xef008000 0x1000>;
457 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
460 				 0xe000 0 0 1 &mpic 2 1
461 				 0xe000 0 0 2 &mpic 3 1>;
465 		bus-range = <0 0>;
466 		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
467 			  0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
472 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
474 			/* IDSEL 0x0 */
475 			0x00000 0 0 1 &mpic 0 1
476 			0x00000 0 0 2 &mpic 1 1
477 			0x00000 0 0 3 &mpic 2 1
478 			0x00000 0 0 4 &mpic 3 1>;
482 		bus-range = <0 0xff>;
483 		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
484 			  0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
489 		reg = <0xef00a000 0x1000>;
492 		pcie@0 {
493 			reg = <0 0 0 0 0>;
497 			ranges = <0x02000000 0 0xc0000000 0x02000000 0
498 			          0xc0000000 0 0x20000000
499 				  0x01000000 0 0x00000000 0x01000000 0
500 				  0x00000000 0 0x08000000>;