Lines Matching +full:0 +full:x1000
37 #size-cells = <0>;
39 PowerPC,8641@0 {
41 reg = <0>;
46 timebase-frequency = <0>; // From uboot
47 bus-frequency = <0>; // From uboot
48 clock-frequency = <0>; // From uboot
57 timebase-frequency = <0>; // From uboot
58 bus-frequency = <0>; // From uboot
59 clock-frequency = <0>; // From uboot
65 reg = <0x00000000 0x20000000>; // 512M at 0x0
72 reg = <0xf8005000 0x1000>;
76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
77 1 0 0xf0000000 0x00010000 // 64KB EEPROM
78 2 0 0xf1000000 0x00100000 // EPLD (1MB)
79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
81 6 0 0xf4000000 0x00100000 // LCD display (1MB)
82 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
84 flash@0,0 {
86 reg = <0 0 0x01000000>;
91 partition@0 {
93 reg = <0x00000000 0x00100000>;
98 reg = <0x00100000 0x00400000>;
103 reg = <0x00500000 0x00a00000>;
107 reg = <0x00f00000 0x00100000>;
112 epld@2,0 {
116 reg = <2 0 0x100000>;
117 ranges = <0 0 5 0 1 // User switches
118 1 0 5 1 1 // Board ID/Rev
119 3 0 5 3 1>; // LEDs
128 ranges = <0x00000000 0xf8000000 0x00100000>;
129 bus-frequency = <0>;
131 mcm-law@0 {
133 reg = <0x0 0x1000>;
139 reg = <0x1000 0x1000>;
146 #size-cells = <0>;
147 cell-index = <0>;
149 reg = <0x3000 0x100>;
157 #size-cells = <0>;
160 reg = <0x3100 0x100>;
170 reg = <0x21300 0x4>;
171 ranges = <0x0 0x21100 0x200>;
172 cell-index = <0>;
173 dma-channel@0 {
176 reg = <0x0 0x80>;
177 cell-index = <0>;
184 reg = <0x80 0x80>;
192 reg = <0x100 0x80>;
200 reg = <0x180 0x80>;
210 cell-index = <0>;
214 reg = <0x24000 0x1000>;
215 ranges = <0x0 0x24000 0x1000>;
225 #size-cells = <0>;
227 reg = <0x520 0x20>;
232 reg = <0x1f>;
235 phy1: ethernet-phy@0 {
238 reg = <0>;
254 reg = <0x11>;
267 reg = <0x25000 0x1000>;
268 ranges = <0x0 0x25000 0x1000>;
278 #size-cells = <0>;
280 reg = <0x520 0x20>;
283 reg = <0x11>;
296 reg = <0x26000 0x1000>;
297 ranges = <0x0 0x26000 0x1000>;
307 #size-cells = <0>;
309 reg = <0x520 0x20>;
312 reg = <0x11>;
325 reg = <0x27000 0x1000>;
326 ranges = <0x0 0x27000 0x1000>;
336 #size-cells = <0>;
338 reg = <0x520 0x20>;
341 reg = <0x11>;
348 cell-index = <0>;
351 reg = <0x4500 0x100>;
352 clock-frequency = <0>;
361 reg = <0x4600 0x100>;
362 clock-frequency = <0>;
368 clock-frequency = <0>;
370 #address-cells = <0>;
372 reg = <0x40000 0x40000>;
380 reg = <0xe0000 0x1000>;
391 reg = <0xf8008000 0x1000>;
392 bus-range = <0x0 0xff>;
393 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
394 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
398 interrupt-map-mask = <0xff00 0 0 7>;
400 /* IDSEL 0x0 */
401 0x0000 0 0 1 &mpic 0 1
402 0x0000 0 0 2 &mpic 1 1
403 0x0000 0 0 3 &mpic 2 1
404 0x0000 0 0 4 &mpic 3 1
407 pcie@0 {
408 reg = <0 0 0 0 0>;
412 ranges = <0x02000000 0x0 0x80000000
413 0x02000000 0x0 0x80000000
414 0x0 0x20000000
416 0x01000000 0x0 0x00000000
417 0x01000000 0x0 0x00000000
418 0x0 0x00100000>;
429 reg = <0xf8009000 0x1000>;
430 bus-range = <0 0xff>;
431 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
432 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
436 interrupt-map-mask = <0xf800 0 0 7>;
438 /* IDSEL 0x0 */
439 0x0000 0 0 1 &mpic 4 1
440 0x0000 0 0 2 &mpic 5 1
441 0x0000 0 0 3 &mpic 6 1
442 0x0000 0 0 4 &mpic 7 1
445 pcie@0 {
446 reg = <0 0 0 0 0>;
450 ranges = <0x02000000 0x0 0xa0000000
451 0x02000000 0x0 0xa0000000
452 0x0 0x20000000
454 0x01000000 0x0 0x00000000
455 0x01000000 0x0 0x00000000
456 0x0 0x00100000>;