Lines Matching +full:0 +full:x1000
35 #size-cells = <0>;
37 PowerPC,8548@0 {
39 reg = <0>;
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
57 ranges = <0x0 0xa0000000 0x100000>;
58 bus-frequency = <0>;
61 ecm-law@0 {
63 reg = <0x0 0x1000>;
69 reg = <0x1000 0x1000>;
76 reg = <0x2000 0x1000>;
83 reg = <0x20000 0x1000>;
85 cache-size = <0x80000>; // L2, 512K
92 #size-cells = <0>;
93 cell-index = <0>;
95 reg = <0x3000 0x100>;
102 reg = <0x48>;
107 reg = <0x68>;
113 #size-cells = <0>;
116 reg = <0x3100 0x100>;
126 reg = <0x21300 0x4>;
127 ranges = <0x0 0x21100 0x200>;
128 cell-index = <0>;
129 dma-channel@0 {
132 reg = <0x0 0x80>;
133 cell-index = <0>;
140 reg = <0x80 0x80>;
148 reg = <0x100 0x80>;
156 reg = <0x180 0x80>;
166 cell-index = <0>;
170 reg = <0x24000 0x1000>;
171 ranges = <0x0 0x24000 0x1000>;
180 #size-cells = <0>;
182 reg = <0x520 0x20>;
184 phy1: ethernet-phy@0 {
215 reg = <0x11>;
228 reg = <0x25000 0x1000>;
229 ranges = <0x0 0x25000 0x1000>;
238 #size-cells = <0>;
240 reg = <0x520 0x20>;
243 reg = <0x11>;
256 reg = <0x26000 0x1000>;
257 ranges = <0x0 0x26000 0x1000>;
266 #size-cells = <0>;
268 reg = <0x520 0x20>;
271 reg = <0x11>;
284 reg = <0x27000 0x1000>;
285 ranges = <0x0 0x27000 0x1000>;
294 #size-cells = <0>;
296 reg = <0x520 0x20>;
299 reg = <0x11>;
306 cell-index = <0>;
309 reg = <0x4500 0x100>; // reg base, size
310 clock-frequency = <0>; // should we fill in in uboot?
320 reg = <0x4600 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot?
329 reg = <0xe0000 0x1000>;
335 #address-cells = <0>;
337 reg = <0x40000 0x40000>;
348 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
354 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
355 2 0x0 0xa3000000 0x00008000 // CAN (2 x CC770)
356 3 0x0 0xa3010000 0x00008000 // NAND FLASH
360 flash@1,0 {
364 reg = <1 0x0 0x8000000>;
368 partition@0 {
370 reg = <0x00000000 0x00200000>;
374 reg = <0x00200000 0x00300000>;
378 reg = <0x00500000 0x07a00000>;
382 reg = <0x07f00000 0x00040000>;
386 reg = <0x07f40000 0x00040000>;
390 reg = <0x07f80000 0x00080000>;
396 can@2,0 {
398 reg = <2 0x0 0x100>;
410 reg = <2 0x100 0x100>;
420 upm@3,0 {
421 #address-cells = <0>;
422 #size-cells = <0>;
424 reg = <3 0x0 0x800>;
425 fsl,upm-addr-offset = <0x10>;
426 fsl,upm-cmd-offset = <0x08>;
428 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
429 fsl,upm-wait-flags = <0x5>;
432 nand@0 {
436 partition@0 {
438 reg = <0x00000000 0x10000000>;
450 reg = <0xa0008000 0x1000>;
452 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
455 0xe000 0 0 1 &mpic 2 1
456 0xe000 0 0 2 &mpic 3 1
457 0xe000 0 0 3 &mpic 6 1
458 0xe000 0 0 4 &mpic 5 1
461 0x5800 0 0 1 &mpic 6 1
462 0x5800 0 0 2 &mpic 5 1
467 bus-range = <0 0>;
468 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
469 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
473 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
475 /* IDSEL 0x0 (PEX) */
476 0x00000 0 0 1 &mpic 0 1
477 0x00000 0 0 2 &mpic 1 1
478 0x00000 0 0 3 &mpic 2 1
479 0x00000 0 0 4 &mpic 3 1>;
483 bus-range = <0 0xff>;
484 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
485 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
490 reg = <0xa000a000 0x1000>;
493 pcie@0 {
494 reg = <0 0 0 0 0>;
498 ranges = <0x02000000 0 0xb0000000 0x02000000 0
499 0xb0000000 0 0x10000000
500 0x01000000 0 0x00000000 0x01000000 0
501 0x00000000 0 0x08000000>;