1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23	model = "Calxeda Highbank";
24	compatible = "calxeda,highbank";
25	#address-cells = <1>;
26	#size-cells = <1>;
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu@0 {
33			compatible = "arm,cortex-a9";
34			reg = <0>;
35			next-level-cache = <&L2>;
36		};
37
38		cpu@1 {
39			compatible = "arm,cortex-a9";
40			reg = <1>;
41			next-level-cache = <&L2>;
42		};
43
44		cpu@2 {
45			compatible = "arm,cortex-a9";
46			reg = <2>;
47			next-level-cache = <&L2>;
48		};
49
50		cpu@3 {
51			compatible = "arm,cortex-a9";
52			reg = <3>;
53			next-level-cache = <&L2>;
54		};
55	};
56
57	memory {
58		name = "memory";
59		device_type = "memory";
60		reg = <0x00000000 0xff900000>;
61	};
62
63	chosen {
64		bootargs = "console=ttyAMA0";
65	};
66
67	soc {
68		#address-cells = <1>;
69		#size-cells = <1>;
70		compatible = "simple-bus";
71		interrupt-parent = <&intc>;
72		ranges;
73
74		timer@fff10600 {
75			compatible = "arm,smp-twd";
76			reg = <0xfff10600 0x20>;
77			interrupts = <1 13 0xf04>;
78		};
79
80		watchdog@fff10620 {
81			compatible = "arm,cortex-a9-wdt";
82			reg = <0xfff10620 0x20>;
83			interrupts = <1 14 0xf04>;
84		};
85
86		intc: interrupt-controller@fff11000 {
87			compatible = "arm,cortex-a9-gic";
88			#interrupt-cells = <3>;
89			#size-cells = <0>;
90			#address-cells = <1>;
91			interrupt-controller;
92			interrupt-parent;
93			reg = <0xfff11000 0x1000>,
94			      <0xfff10100 0x100>;
95		};
96
97		L2: l2-cache {
98			compatible = "arm,pl310-cache";
99			reg = <0xfff12000 0x1000>;
100			interrupts = <0 70 4>;
101			cache-unified;
102			cache-level = <2>;
103		};
104
105		pmu {
106			compatible = "arm,cortex-a9-pmu";
107			interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
108		};
109
110		sata@ffe08000 {
111			compatible = "calxeda,hb-ahci";
112			reg = <0xffe08000 0x10000>;
113			interrupts = <0 83 4>;
114		};
115
116		sdhci@ffe0e000 {
117			compatible = "calxeda,hb-sdhci";
118			reg = <0xffe0e000 0x1000>;
119			interrupts = <0 90 4>;
120		};
121
122		ipc@fff20000 {
123			compatible = "arm,pl320", "arm,primecell";
124			reg = <0xfff20000 0x1000>;
125			interrupts = <0 7 4>;
126		};
127
128		gpioe: gpio@fff30000 {
129			#gpio-cells = <2>;
130			compatible = "arm,pl061", "arm,primecell";
131			gpio-controller;
132			reg = <0xfff30000 0x1000>;
133			interrupts = <0 14 4>;
134		};
135
136		gpiof: gpio@fff31000 {
137			#gpio-cells = <2>;
138			compatible = "arm,pl061", "arm,primecell";
139			gpio-controller;
140			reg = <0xfff31000 0x1000>;
141			interrupts = <0 15 4>;
142		};
143
144		gpiog: gpio@fff32000 {
145			#gpio-cells = <2>;
146			compatible = "arm,pl061", "arm,primecell";
147			gpio-controller;
148			reg = <0xfff32000 0x1000>;
149			interrupts = <0 16 4>;
150		};
151
152		gpioh: gpio@fff33000 {
153			#gpio-cells = <2>;
154			compatible = "arm,pl061", "arm,primecell";
155			gpio-controller;
156			reg = <0xfff33000 0x1000>;
157			interrupts = <0 17 4>;
158		};
159
160		timer {
161			compatible = "arm,sp804", "arm,primecell";
162			reg = <0xfff34000 0x1000>;
163			interrupts = <0 18 4>;
164		};
165
166		rtc@fff35000 {
167			compatible = "arm,pl031", "arm,primecell";
168			reg = <0xfff35000 0x1000>;
169			interrupts = <0 19 4>;
170		};
171
172		serial@fff36000 {
173			compatible = "arm,pl011", "arm,primecell";
174			reg = <0xfff36000 0x1000>;
175			interrupts = <0 20 4>;
176		};
177
178		smic@fff3a000 {
179			compatible = "ipmi-smic";
180			device_type = "ipmi";
181			reg = <0xfff3a000 0x1000>;
182			interrupts = <0 24 4>;
183			reg-size = <4>;
184			reg-spacing = <4>;
185		};
186
187		sregs@fff3c000 {
188			compatible = "calxeda,hb-sregs";
189			reg = <0xfff3c000 0x1000>;
190		};
191
192		dma@fff3d000 {
193			compatible = "arm,pl330", "arm,primecell";
194			reg = <0xfff3d000 0x1000>;
195			interrupts = <0 92 4>;
196		};
197
198		ethernet@fff50000 {
199			compatible = "calxeda,hb-xgmac";
200			reg = <0xfff50000 0x1000>;
201			interrupts = <0 77 4  0 78 4  0 79 4>;
202		};
203
204		ethernet@fff51000 {
205			compatible = "calxeda,hb-xgmac";
206			reg = <0xfff51000 0x1000>;
207			interrupts = <0 80 4  0 81 4  0 82 4>;
208		};
209	};
210};
211