Lines Matching +full:0 +full:x1000
20 /memreserve/ 0x00000000 0x0001000;
30 #size-cells = <0>;
32 cpu@0 {
34 reg = <0>;
60 reg = <0x00000000 0xff900000>;
76 reg = <0xfff10600 0x20>;
77 interrupts = <1 13 0xf04>;
82 reg = <0xfff10620 0x20>;
83 interrupts = <1 14 0xf04>;
89 #size-cells = <0>;
93 reg = <0xfff11000 0x1000>,
94 <0xfff10100 0x100>;
99 reg = <0xfff12000 0x1000>;
100 interrupts = <0 70 4>;
107 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
112 reg = <0xffe08000 0x10000>;
113 interrupts = <0 83 4>;
118 reg = <0xffe0e000 0x1000>;
119 interrupts = <0 90 4>;
124 reg = <0xfff20000 0x1000>;
125 interrupts = <0 7 4>;
132 reg = <0xfff30000 0x1000>;
133 interrupts = <0 14 4>;
140 reg = <0xfff31000 0x1000>;
141 interrupts = <0 15 4>;
148 reg = <0xfff32000 0x1000>;
149 interrupts = <0 16 4>;
156 reg = <0xfff33000 0x1000>;
157 interrupts = <0 17 4>;
162 reg = <0xfff34000 0x1000>;
163 interrupts = <0 18 4>;
168 reg = <0xfff35000 0x1000>;
169 interrupts = <0 19 4>;
174 reg = <0xfff36000 0x1000>;
175 interrupts = <0 20 4>;
181 reg = <0xfff3a000 0x1000>;
182 interrupts = <0 24 4>;
189 reg = <0xfff3c000 0x1000>;
194 reg = <0xfff3d000 0x1000>;
195 interrupts = <0 92 4>;
200 reg = <0xfff50000 0x1000>;
201 interrupts = <0 77 4 0 78 4 0 79 4>;
206 reg = <0xfff51000 0x1000>;
207 interrupts = <0 80 4 0 81 4 0 82 4>;