Lines Matching +full:0 +full:x1000
17 #define SOC_ID_DANUBE1 0x129
18 #define SOC_ID_DANUBE2 0x12B
19 #define SOC_ID_TWINPASS 0x12D
20 #define SOC_ID_AMAZON_SE 0x152
21 #define SOC_ID_ARX188 0x16C
22 #define SOC_ID_ARX168 0x16D
23 #define SOC_ID_ARX182 0x16F
26 #define SOC_TYPE_DANUBE 0x01
27 #define SOC_TYPE_TWINPASS 0x02
28 #define SOC_TYPE_AR9 0x03
29 #define SOC_TYPE_VR9 0x04
30 #define SOC_TYPE_AMAZON_SE 0x05
33 #define LTQ_ASC0_BASE_ADDR 0x1E100400
34 #define LTQ_ASC1_BASE_ADDR 0x1E100C00
35 #define LTQ_ASC_SIZE 0x400
38 #define LTQ_RCU_BASE_ADDR 0x1F203000
39 #define LTQ_RCU_SIZE 0x1000
42 #define LTQ_GPTU_BASE_ADDR 0x18000300
43 #define LTQ_GPTU_SIZE 0x100
46 #define LTQ_EBU_GPIO_START 0x14000000
47 #define LTQ_EBU_GPIO_SIZE 0x1000
49 #define LTQ_EBU_BASE_ADDR 0x1E105300
50 #define LTQ_EBU_SIZE 0x100
52 #define LTQ_EBU_BUSCON0 0x0060
53 #define LTQ_EBU_PCC_CON 0x0090
54 #define LTQ_EBU_PCC_IEN 0x00A4
55 #define LTQ_EBU_PCC_ISTAT 0x00A0
56 #define LTQ_EBU_BUSCON1 0x0064
57 #define LTQ_EBU_ADDRSEL1 0x0024
58 #define EBU_WRDIS 0x80000000
61 #define LTQ_CGU_BASE_ADDR 0x1F103000
62 #define LTQ_CGU_SIZE 0x1000
65 #define LTQ_ICU_BASE_ADDR 0x1F880200
66 #define LTQ_ICU_SIZE 0x100
69 #define LTQ_EIU_BASE_ADDR 0x1F101000
70 #define LTQ_EIU_SIZE 0x1000
73 #define LTQ_PMU_BASE_ADDR 0x1F102000
74 #define LTQ_PMU_SIZE 0x1000
76 #define PMU_DMA 0x0020
77 #define PMU_USB 0x8041
78 #define PMU_LED 0x0800
79 #define PMU_GPT 0x1000
80 #define PMU_PPE 0x2000
81 #define PMU_FPI 0x4000
82 #define PMU_SWITCH 0x10000000
85 #define LTQ_ETOP_BASE_ADDR 0x1E180000
86 #define LTQ_ETOP_SIZE 0x40000
89 #define LTQ_DMA_BASE_ADDR 0x1E104100
90 #define LTQ_DMA_SIZE 0x800
93 #define PCI_CR_BASE_ADDR 0x1E105400
94 #define PCI_CR_SIZE 0x400
97 #define LTQ_WDT_BASE_ADDR 0x1F8803F0
98 #define LTQ_WDT_SIZE 0x10
101 #define LTQ_STP_BASE_ADDR 0x1E100BB0
102 #define LTQ_STP_SIZE 0x40
105 #define LTQ_GPIO0_BASE_ADDR 0x1E100B10
106 #define LTQ_GPIO1_BASE_ADDR 0x1E100B40
107 #define LTQ_GPIO2_BASE_ADDR 0x1E100B70
108 #define LTQ_GPIO_SIZE 0x30
111 #define LTQ_SSC_BASE_ADDR 0x1e100800
112 #define LTQ_SSC_SIZE 0x100
115 #define LTQ_MEI_BASE_ADDR 0x1E116000
118 #define LTQ_DEU_BASE_ADDR 0x1E103100
121 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
122 #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))