boot/dts/xpedite5200.dts

33 		#size-cells = <0>;
35 		PowerPC,8548@0 {
37 			reg = <0>;
40 			d-cache-size = <0x8000>;	// L1, 32K
41 			i-cache-size = <0x8000>;	// L1, 32K
48 		reg = <0x0 0x0>;	// Filled in by U-Boot
55 		ranges = <0x0 0xef000000 0x100000>;
56 		bus-frequency = <0>;
59 		ecm-law@0 {
61 			reg = <0x0 0x1000>;
67 			reg = <0x1000 0x1000>;
74 			reg = <0x2000 0x1000>;
81 			reg = <0x20000 0x1000>;
83 			cache-size = <0x80000>;	// L2, 512K
91 			#size-cells = <0>;
92 			cell-index = <0>;
94 			reg = <0x3000 0x100>;
101 			 * 	0: BRD_CFG0 (1: P14 IO present)
112 				reg = <0x18>;
115 				polarity = <0x00>;
121 				reg = <0x19>;
124 				polarity = <0x00>;
129 				reg = <0x50>;
135 				reg = <0x68>;
140 				reg = <0x34>;
147 			#size-cells = <0>;
150 			reg = <0x3100 0x100>;
160 			reg = <0x21300 0x4>;
161 			ranges = <0x0 0x21100 0x200>;
162 			cell-index = <0>;
163 			dma-channel@0 {
166 				reg = <0x0 0x80>;
167 				cell-index = <0>;
174 				reg = <0x80 0x80>;
182 				reg = <0x100 0x80>;
190 				reg = <0x180 0x80>;
197 		/* eTSEC1: Front panel port 0 */
201 			cell-index = <0>;
205 			reg = <0x24000 0x1000>;
206 			ranges = <0x0 0x24000 0x1000>;
215 				#size-cells = <0>;
217 				reg = <0x520 0x20>;
222 					reg = <0x1>;
227 					reg = <0x2>;
232 					reg = <0x3>;
237 					reg = <0x4>;
240 					reg = <0x11>;
254 			reg = <0x25000 0x1000>;
255 			ranges = <0x0 0x25000 0x1000>;
264 				#size-cells = <0>;
266 				reg = <0x520 0x20>;
269 					reg = <0x11>;
283 			reg = <0x26000 0x1000>;
284 			ranges = <0x0 0x26000 0x1000>;
293 				#size-cells = <0>;
295 				reg = <0x520 0x20>;
298 					reg = <0x11>;
312 			reg = <0x27000 0x1000>;
313 			ranges = <0x0 0x27000 0x1000>;
322 				#size-cells = <0>;
324 				reg = <0x520 0x20>;
327 					reg = <0x11>;
334 			cell-index = <0>;
337 			reg = <0x4500 0x100>;
338 			clock-frequency = <0>;
348 			reg = <0x4600 0x100>;
349 			clock-frequency = <0>;
357 			reg = <0xe0000 0x1000>;
363 			#address-cells = <0>;
365 			reg = <0x40000 0x40000>;
376 		reg = <0xef005000 0x100>;	// BRx, ORx, etc.
381 			0 0x0 0xfc000000 0x04000000	// NOR boot flash
382 			1 0x0 0xf8000000 0x04000000	// NOR expansion flash
383 			2 0x0 0xef800000 0x00010000	// NAND CE1
384 			3 0x0 0xef840000 0x00010000	// NAND CE2
387 		nor-boot@0,0 {
391 			reg = <0 0x0 0x4000000>;
394 			partition@0 {
396 				reg = <0x00000000 0x180000>;
400 				reg = <0x00180000 0x180000>;
404 				reg = <0x00300000 0x3c80000>;
408 				reg = <0x03f80000 0x80000>;
412 		nor-alternate@1,0 {
416 			reg = <1 0x0 0x4000000>;
419 			partition@0 {
421 				reg = <0x00000000 0x3f80000>;
425 				reg = <0x03f80000 0x80000>;
429 		nand@2,0 {
433 			reg = <2 0x0 0x10000>;
434 			cle-line = <0x8>;	/* CLE tied to A3 */
435 			ale-line = <0x10>;	/* ALE tied to A4 */
438 			partition@0 {
440 				reg = <0 0x40000000>;
452 		reg = <0xef008000 0x1000>;
454 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
457 				 0xe000 0 0 1 &mpic 2 1
458 				 0xe000 0 0 2 &mpic 3 1>;
462 		bus-range = <0 0>;
463 		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
464 			  0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;